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586 lines
20 KiB
C
586 lines
20 KiB
C
/*
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* QEMU PowerPC PowerNV Emulation of some ChipTOD behaviour
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*
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* Copyright (c) 2022-2023, IBM Corporation.
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*
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* ChipTOD (aka TOD) is a facility implemented in the nest / pervasive. The
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* purpose is to keep time-of-day across chips and cores.
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*
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* There is a master chip TOD, which sends signals to slave chip TODs to
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* keep them synchronized. There are two sets of configuration registers
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* called primary and secondary, which can be used fail over.
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*
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* The chip TOD also distributes synchronisation signals to the timebase
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* facility in each of the cores on the chip. In particular there is a
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* feature that can move the TOD value in the ChipTOD to and from the TB.
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*
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* Initialisation typically brings all ChipTOD into sync (see tod_state),
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* and then brings each core TB into sync with the ChipTODs (see timebase
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* state and TFMR). This model is a very basic simulation of the init sequence
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* performed by skiboot.
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*/
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#include "qemu/osdep.h"
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#include "sysemu/reset.h"
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#include "target/ppc/cpu.h"
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#include "qapi/error.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "hw/irq.h"
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#include "hw/qdev-properties.h"
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#include "hw/ppc/fdt.h"
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#include "hw/ppc/ppc.h"
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#include "hw/ppc/pnv.h"
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#include "hw/ppc/pnv_chip.h"
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#include "hw/ppc/pnv_core.h"
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#include "hw/ppc/pnv_xscom.h"
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#include "hw/ppc/pnv_chiptod.h"
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#include "trace.h"
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#include <libfdt.h>
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/* TOD chip XSCOM addresses */
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#define TOD_M_PATH_CTRL_REG 0x00000000 /* Master Path ctrl reg */
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#define TOD_PRI_PORT_0_CTRL_REG 0x00000001 /* Primary port0 ctrl reg */
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#define TOD_PRI_PORT_1_CTRL_REG 0x00000002 /* Primary port1 ctrl reg */
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#define TOD_SEC_PORT_0_CTRL_REG 0x00000003 /* Secondary p0 ctrl reg */
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#define TOD_SEC_PORT_1_CTRL_REG 0x00000004 /* Secondary p1 ctrl reg */
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#define TOD_S_PATH_CTRL_REG 0x00000005 /* Slave Path ctrl reg */
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#define TOD_I_PATH_CTRL_REG 0x00000006 /* Internal Path ctrl reg */
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/* -- TOD primary/secondary master/slave control register -- */
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#define TOD_PSS_MSS_CTRL_REG 0x00000007
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/* -- TOD primary/secondary master/slave status register -- */
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#define TOD_PSS_MSS_STATUS_REG 0x00000008
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/* TOD chip XSCOM addresses */
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#define TOD_CHIP_CTRL_REG 0x00000010 /* Chip control reg */
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#define TOD_TX_TTYPE_0_REG 0x00000011
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#define TOD_TX_TTYPE_1_REG 0x00000012 /* PSS switch reg */
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#define TOD_TX_TTYPE_2_REG 0x00000013 /* Enable step checkers */
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#define TOD_TX_TTYPE_3_REG 0x00000014 /* Request TOD reg */
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#define TOD_TX_TTYPE_4_REG 0x00000015 /* Send TOD reg */
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#define TOD_TX_TTYPE_5_REG 0x00000016 /* Invalidate TOD reg */
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#define TOD_MOVE_TOD_TO_TB_REG 0x00000017
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#define TOD_LOAD_TOD_MOD_REG 0x00000018
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#define TOD_LOAD_TOD_REG 0x00000021
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#define TOD_START_TOD_REG 0x00000022
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#define TOD_FSM_REG 0x00000024
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#define TOD_TX_TTYPE_CTRL_REG 0x00000027 /* TX TTYPE Control reg */
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#define TOD_TX_TTYPE_PIB_SLAVE_ADDR PPC_BITMASK(26, 31)
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/* -- TOD Error interrupt register -- */
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#define TOD_ERROR_REG 0x00000030
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/* PC unit PIB address which recieves the timebase transfer from TOD */
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#define PC_TOD 0x4A3
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/*
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* The TOD FSM:
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* - The reset state is 0 error.
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* - A hardware error detected will transition to state 0 from any state.
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* - LOAD_TOD_MOD and TTYPE5 will transition to state 7 from any state.
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*
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* | state | action | new |
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* |------------+------------------------------+-----|
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* | 0 error | LOAD_TOD_MOD | 7 |
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* | 0 error | Recv TTYPE5 (invalidate TOD) | 7 |
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* | 7 not_set | LOAD_TOD (bit-63 = 0) | 2 |
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* | 7 not_set | LOAD_TOD (bit-63 = 1) | 1 |
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* | 7 not_set | Recv TTYPE4 (send TOD) | 2 |
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* | 2 running | | |
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* | 1 stopped | START_TOD | 2 |
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*
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* Note the hardware has additional states but they relate to the sending
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* and receiving and waiting on synchronisation signals between chips and
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* are not described or modeled here.
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*/
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static uint64_t pnv_chiptod_xscom_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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PnvChipTOD *chiptod = PNV_CHIPTOD(opaque);
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uint32_t offset = addr >> 3;
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uint64_t val = 0;
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switch (offset) {
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case TOD_PSS_MSS_STATUS_REG:
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/*
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* ChipTOD does not support configurations other than primary
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* master, does not support errors, etc.
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*/
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val |= PPC_BITMASK(6, 10); /* STEP checker validity */
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val |= PPC_BIT(12); /* Primary config master path select */
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if (chiptod->tod_state == tod_running) {
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val |= PPC_BIT(20); /* Is running */
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}
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val |= PPC_BIT(21); /* Is using primary config */
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val |= PPC_BIT(26); /* Is using master path select */
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if (chiptod->primary) {
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val |= PPC_BIT(23); /* Is active master */
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} else if (chiptod->secondary) {
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val |= PPC_BIT(24); /* Is backup master */
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} else {
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val |= PPC_BIT(25); /* Is slave (should backup master set this?) */
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}
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break;
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case TOD_PSS_MSS_CTRL_REG:
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val = chiptod->pss_mss_ctrl_reg;
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break;
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case TOD_TX_TTYPE_CTRL_REG:
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val = 0;
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break;
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case TOD_ERROR_REG:
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val = chiptod->tod_error;
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break;
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case TOD_FSM_REG:
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if (chiptod->tod_state == tod_running) {
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val |= PPC_BIT(4);
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}
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break;
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default:
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qemu_log_mask(LOG_UNIMP, "pnv_chiptod: unimplemented register: Ox%"
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HWADDR_PRIx "\n", addr >> 3);
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}
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trace_pnv_chiptod_xscom_read(addr >> 3, val);
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return val;
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}
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static void chiptod_receive_ttype(PnvChipTOD *chiptod, uint32_t trigger)
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{
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switch (trigger) {
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case TOD_TX_TTYPE_4_REG:
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if (chiptod->tod_state != tod_not_set) {
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qemu_log_mask(LOG_GUEST_ERROR, "pnv_chiptod: received TTYPE4 in "
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" state %d, should be in 7 (TOD_NOT_SET)\n",
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chiptod->tod_state);
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} else {
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chiptod->tod_state = tod_running;
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}
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break;
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case TOD_TX_TTYPE_5_REG:
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/* Works from any state */
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chiptod->tod_state = tod_not_set;
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break;
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default:
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qemu_log_mask(LOG_UNIMP, "pnv_chiptod: received unimplemented "
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" TTYPE %u\n", trigger);
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break;
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}
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}
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static void chiptod_power9_broadcast_ttype(PnvChipTOD *sender,
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uint32_t trigger)
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{
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PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
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int i;
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for (i = 0; i < pnv->num_chips; i++) {
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Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]);
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PnvChipTOD *chiptod = &chip9->chiptod;
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if (chiptod != sender) {
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chiptod_receive_ttype(chiptod, trigger);
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}
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}
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}
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static void chiptod_power10_broadcast_ttype(PnvChipTOD *sender,
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uint32_t trigger)
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{
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PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
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int i;
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for (i = 0; i < pnv->num_chips; i++) {
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Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]);
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PnvChipTOD *chiptod = &chip10->chiptod;
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if (chiptod != sender) {
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chiptod_receive_ttype(chiptod, trigger);
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}
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}
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}
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static PnvCore *pnv_chip_get_core_by_xscom_base(PnvChip *chip,
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uint32_t xscom_base)
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{
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PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
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int i;
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for (i = 0; i < chip->nr_cores; i++) {
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PnvCore *pc = chip->cores[i];
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CPUCore *cc = CPU_CORE(pc);
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int core_hwid = cc->core_id;
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if (pcc->xscom_core_base(chip, core_hwid) == xscom_base) {
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return pc;
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}
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}
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return NULL;
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}
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static PnvCore *chiptod_power9_tx_ttype_target(PnvChipTOD *chiptod,
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uint64_t val)
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{
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/*
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* skiboot uses Core ID for P9, though SCOM should work too.
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*/
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if (val & PPC_BIT(35)) { /* SCOM addressing */
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uint32_t addr = val >> 32;
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uint32_t reg = addr & 0xfff;
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if (reg != PC_TOD) {
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qemu_log_mask(LOG_GUEST_ERROR, "pnv_chiptod: SCOM addressing: "
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"unimplemented slave register 0x%" PRIx32 "\n", reg);
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return NULL;
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}
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return pnv_chip_get_core_by_xscom_base(chiptod->chip, addr & ~0xfff);
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} else { /* Core ID addressing */
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uint32_t core_id = GETFIELD(TOD_TX_TTYPE_PIB_SLAVE_ADDR, val) & 0x1f;
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return pnv_chip_find_core(chiptod->chip, core_id);
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}
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}
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static PnvCore *chiptod_power10_tx_ttype_target(PnvChipTOD *chiptod,
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uint64_t val)
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{
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/*
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* skiboot uses SCOM for P10 because Core ID was unable to be made to
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* work correctly. For this reason only SCOM addressing is implemented.
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*/
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if (val & PPC_BIT(35)) { /* SCOM addressing */
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uint32_t addr = val >> 32;
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uint32_t reg = addr & 0xfff;
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if (reg != PC_TOD) {
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qemu_log_mask(LOG_GUEST_ERROR, "pnv_chiptod: SCOM addressing: "
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"unimplemented slave register 0x%" PRIx32 "\n", reg);
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return NULL;
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}
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/*
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* This may not deal with P10 big-core addressing at the moment.
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* The big-core code in skiboot syncs small cores, but it targets
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* the even PIR (first small-core) when syncing second small-core.
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*/
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return pnv_chip_get_core_by_xscom_base(chiptod->chip, addr & ~0xfff);
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} else { /* Core ID addressing */
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qemu_log_mask(LOG_UNIMP, "pnv_chiptod: TX TTYPE Core ID "
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"addressing is not implemented for POWER10\n");
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return NULL;
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}
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}
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static void pnv_chiptod_xscom_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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PnvChipTOD *chiptod = PNV_CHIPTOD(opaque);
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PnvChipTODClass *pctc = PNV_CHIPTOD_GET_CLASS(chiptod);
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uint32_t offset = addr >> 3;
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trace_pnv_chiptod_xscom_write(addr >> 3, val);
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switch (offset) {
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case TOD_PSS_MSS_CTRL_REG:
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/* Is this correct? */
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if (chiptod->primary) {
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val |= PPC_BIT(1); /* TOD is master */
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} else {
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val &= ~PPC_BIT(1);
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}
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val |= PPC_BIT(2); /* Drawer is master (don't simulate multi-drawer) */
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chiptod->pss_mss_ctrl_reg = val & PPC_BITMASK(0, 31);
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break;
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case TOD_TX_TTYPE_CTRL_REG:
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/*
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* This register sets the target of the TOD value transfer initiated
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* by TOD_MOVE_TOD_TO_TB. The TOD is able to send the address to
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* any target register, though in practice only the PC TOD register
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* should be used. ChipTOD has a "SCOM addressing" mode which fully
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* specifies the SCOM address, and a core-ID mode which uses the
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* core ID to target the PC TOD for a given core.
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*/
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chiptod->slave_pc_target = pctc->tx_ttype_target(chiptod, val);
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if (!chiptod->slave_pc_target) {
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qemu_log_mask(LOG_GUEST_ERROR, "pnv_chiptod: xscom write reg"
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" TOD_TX_TTYPE_CTRL_REG val 0x%" PRIx64
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" invalid slave address\n", val);
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}
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break;
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case TOD_ERROR_REG:
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chiptod->tod_error &= ~val;
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break;
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case TOD_LOAD_TOD_MOD_REG:
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if (!(val & PPC_BIT(0))) {
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qemu_log_mask(LOG_GUEST_ERROR, "pnv_chiptod: xscom write reg"
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" TOD_LOAD_TOD_MOD_REG with bad val 0x%" PRIx64"\n",
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val);
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} else {
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chiptod->tod_state = tod_not_set;
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}
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break;
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case TOD_LOAD_TOD_REG:
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if (chiptod->tod_state != tod_not_set) {
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qemu_log_mask(LOG_GUEST_ERROR, "pnv_chiptod: LOAD_TOG_REG in "
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" state %d, should be in 7 (TOD_NOT_SET)\n",
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chiptod->tod_state);
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} else {
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if (val & PPC_BIT(63)) {
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chiptod->tod_state = tod_stopped;
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} else {
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chiptod->tod_state = tod_running;
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}
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}
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break;
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case TOD_MOVE_TOD_TO_TB_REG:
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/*
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* XXX: it should be a cleaner model to have this drive a SCOM
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* transaction to the target address, and implement the state machine
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* in the PnvCore. For now, this hack makes things work.
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*/
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if (chiptod->tod_state != tod_running) {
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qemu_log_mask(LOG_GUEST_ERROR, "pnv_chiptod: xscom write reg"
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" TOD_MOVE_TOD_TO_TB_REG in bad state %d\n",
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chiptod->tod_state);
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} else if (!(val & PPC_BIT(0))) {
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qemu_log_mask(LOG_GUEST_ERROR, "pnv_chiptod: xscom write reg"
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" TOD_MOVE_TOD_TO_TB_REG with bad val 0x%" PRIx64"\n",
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val);
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} else if (chiptod->slave_pc_target == NULL) {
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qemu_log_mask(LOG_GUEST_ERROR, "pnv_chiptod: xscom write reg"
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" TOD_MOVE_TOD_TO_TB_REG with no slave target\n");
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} else {
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PnvCore *pc = chiptod->slave_pc_target;
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/*
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* Moving TOD to TB will set the TB of all threads in a
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* core, so skiboot only does this once per thread0, so
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* that is where we keep the timebase state machine.
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*
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* It is likely possible for TBST to be driven from other
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* threads in the core, but for now we only implement it for
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* thread 0.
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*/
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if (pc->tod_state.tb_ready_for_tod) {
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pc->tod_state.tod_sent_to_tb = 1;
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} else {
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qemu_log_mask(LOG_GUEST_ERROR, "pnv_chiptod: xscom write reg"
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" TOD_MOVE_TOD_TO_TB_REG with TB not ready to"
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" receive TOD\n");
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}
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}
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break;
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case TOD_START_TOD_REG:
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if (chiptod->tod_state != tod_stopped) {
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qemu_log_mask(LOG_GUEST_ERROR, "pnv_chiptod: LOAD_TOG_REG in "
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" state %d, should be in 1 (TOD_STOPPED)\n",
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chiptod->tod_state);
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} else {
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chiptod->tod_state = tod_running;
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}
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break;
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case TOD_TX_TTYPE_4_REG:
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case TOD_TX_TTYPE_5_REG:
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pctc->broadcast_ttype(chiptod, offset);
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break;
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default:
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qemu_log_mask(LOG_UNIMP, "pnv_chiptod: unimplemented register: Ox%"
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HWADDR_PRIx "\n", addr >> 3);
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}
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}
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static const MemoryRegionOps pnv_chiptod_xscom_ops = {
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.read = pnv_chiptod_xscom_read,
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.write = pnv_chiptod_xscom_write,
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.valid.min_access_size = 8,
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.valid.max_access_size = 8,
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.impl.min_access_size = 8,
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.impl.max_access_size = 8,
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.endianness = DEVICE_BIG_ENDIAN,
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};
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static int pnv_chiptod_dt_xscom(PnvXScomInterface *dev, void *fdt,
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int xscom_offset,
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const char compat[], size_t compat_size)
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{
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PnvChipTOD *chiptod = PNV_CHIPTOD(dev);
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g_autofree char *name = NULL;
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int offset;
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uint32_t chiptod_pcba = PNV9_XSCOM_CHIPTOD_BASE;
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uint32_t reg[] = {
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cpu_to_be32(chiptod_pcba),
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cpu_to_be32(PNV9_XSCOM_CHIPTOD_SIZE)
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};
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name = g_strdup_printf("chiptod@%x", chiptod_pcba);
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offset = fdt_add_subnode(fdt, xscom_offset, name);
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_FDT(offset);
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if (chiptod->primary) {
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_FDT((fdt_setprop(fdt, offset, "primary", NULL, 0)));
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} else if (chiptod->secondary) {
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_FDT((fdt_setprop(fdt, offset, "secondary", NULL, 0)));
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}
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_FDT((fdt_setprop(fdt, offset, "reg", reg, sizeof(reg))));
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_FDT((fdt_setprop(fdt, offset, "compatible", compat, compat_size)));
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return 0;
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}
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static int pnv_chiptod_power9_dt_xscom(PnvXScomInterface *dev, void *fdt,
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int xscom_offset)
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{
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const char compat[] = "ibm,power-chiptod\0ibm,power9-chiptod";
|
|
|
|
return pnv_chiptod_dt_xscom(dev, fdt, xscom_offset, compat, sizeof(compat));
|
|
}
|
|
|
|
static Property pnv_chiptod_properties[] = {
|
|
DEFINE_PROP_BOOL("primary", PnvChipTOD, primary, false),
|
|
DEFINE_PROP_BOOL("secondary", PnvChipTOD, secondary, false),
|
|
DEFINE_PROP_LINK("chip", PnvChipTOD , chip, TYPE_PNV_CHIP, PnvChip *),
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
};
|
|
|
|
static void pnv_chiptod_power9_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
PnvChipTODClass *pctc = PNV_CHIPTOD_CLASS(klass);
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
PnvXScomInterfaceClass *xdc = PNV_XSCOM_INTERFACE_CLASS(klass);
|
|
|
|
dc->desc = "PowerNV ChipTOD Controller (POWER9)";
|
|
device_class_set_props(dc, pnv_chiptod_properties);
|
|
|
|
xdc->dt_xscom = pnv_chiptod_power9_dt_xscom;
|
|
|
|
pctc->broadcast_ttype = chiptod_power9_broadcast_ttype;
|
|
pctc->tx_ttype_target = chiptod_power9_tx_ttype_target;
|
|
|
|
pctc->xscom_size = PNV_XSCOM_CHIPTOD_SIZE;
|
|
}
|
|
|
|
static const TypeInfo pnv_chiptod_power9_type_info = {
|
|
.name = TYPE_PNV9_CHIPTOD,
|
|
.parent = TYPE_PNV_CHIPTOD,
|
|
.instance_size = sizeof(PnvChipTOD),
|
|
.class_init = pnv_chiptod_power9_class_init,
|
|
.interfaces = (InterfaceInfo[]) {
|
|
{ TYPE_PNV_XSCOM_INTERFACE },
|
|
{ }
|
|
}
|
|
};
|
|
|
|
static int pnv_chiptod_power10_dt_xscom(PnvXScomInterface *dev, void *fdt,
|
|
int xscom_offset)
|
|
{
|
|
const char compat[] = "ibm,power-chiptod\0ibm,power10-chiptod";
|
|
|
|
return pnv_chiptod_dt_xscom(dev, fdt, xscom_offset, compat, sizeof(compat));
|
|
}
|
|
|
|
static void pnv_chiptod_power10_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
PnvChipTODClass *pctc = PNV_CHIPTOD_CLASS(klass);
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
PnvXScomInterfaceClass *xdc = PNV_XSCOM_INTERFACE_CLASS(klass);
|
|
|
|
dc->desc = "PowerNV ChipTOD Controller (POWER10)";
|
|
device_class_set_props(dc, pnv_chiptod_properties);
|
|
|
|
xdc->dt_xscom = pnv_chiptod_power10_dt_xscom;
|
|
|
|
pctc->broadcast_ttype = chiptod_power10_broadcast_ttype;
|
|
pctc->tx_ttype_target = chiptod_power10_tx_ttype_target;
|
|
|
|
pctc->xscom_size = PNV_XSCOM_CHIPTOD_SIZE;
|
|
}
|
|
|
|
static const TypeInfo pnv_chiptod_power10_type_info = {
|
|
.name = TYPE_PNV10_CHIPTOD,
|
|
.parent = TYPE_PNV_CHIPTOD,
|
|
.instance_size = sizeof(PnvChipTOD),
|
|
.class_init = pnv_chiptod_power10_class_init,
|
|
.interfaces = (InterfaceInfo[]) {
|
|
{ TYPE_PNV_XSCOM_INTERFACE },
|
|
{ }
|
|
}
|
|
};
|
|
|
|
static void pnv_chiptod_reset(void *dev)
|
|
{
|
|
PnvChipTOD *chiptod = PNV_CHIPTOD(dev);
|
|
|
|
chiptod->pss_mss_ctrl_reg = 0;
|
|
if (chiptod->primary) {
|
|
chiptod->pss_mss_ctrl_reg |= PPC_BIT(1); /* TOD is master */
|
|
}
|
|
/* Drawer is master (we do not simulate multi-drawer) */
|
|
chiptod->pss_mss_ctrl_reg |= PPC_BIT(2);
|
|
|
|
chiptod->tod_error = 0;
|
|
chiptod->tod_state = tod_error;
|
|
}
|
|
|
|
static void pnv_chiptod_realize(DeviceState *dev, Error **errp)
|
|
{
|
|
PnvChipTOD *chiptod = PNV_CHIPTOD(dev);
|
|
PnvChipTODClass *pctc = PNV_CHIPTOD_GET_CLASS(chiptod);
|
|
|
|
/* XScom regions for ChipTOD registers */
|
|
pnv_xscom_region_init(&chiptod->xscom_regs, OBJECT(dev),
|
|
&pnv_chiptod_xscom_ops, chiptod, "xscom-chiptod",
|
|
pctc->xscom_size);
|
|
|
|
qemu_register_reset(pnv_chiptod_reset, chiptod);
|
|
}
|
|
|
|
static void pnv_chiptod_unrealize(DeviceState *dev)
|
|
{
|
|
PnvChipTOD *chiptod = PNV_CHIPTOD(dev);
|
|
|
|
qemu_unregister_reset(pnv_chiptod_reset, chiptod);
|
|
}
|
|
|
|
static void pnv_chiptod_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
dc->realize = pnv_chiptod_realize;
|
|
dc->unrealize = pnv_chiptod_unrealize;
|
|
dc->desc = "PowerNV ChipTOD Controller";
|
|
dc->user_creatable = false;
|
|
}
|
|
|
|
static const TypeInfo pnv_chiptod_type_info = {
|
|
.name = TYPE_PNV_CHIPTOD,
|
|
.parent = TYPE_DEVICE,
|
|
.instance_size = sizeof(PnvChipTOD),
|
|
.class_init = pnv_chiptod_class_init,
|
|
.class_size = sizeof(PnvChipTODClass),
|
|
.abstract = true,
|
|
};
|
|
|
|
static void pnv_chiptod_register_types(void)
|
|
{
|
|
type_register_static(&pnv_chiptod_type_info);
|
|
type_register_static(&pnv_chiptod_power9_type_info);
|
|
type_register_static(&pnv_chiptod_power10_type_info);
|
|
}
|
|
|
|
type_init(pnv_chiptod_register_types);
|