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1056 lines
36 KiB
C
1056 lines
36 KiB
C
/*
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* QEMU PowerPC CHRP (Genesi/bPlan Pegasos I/II) hardware System Emulator
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*
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* Copyright (c) 2018-2021 BALATON Zoltan
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*
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* This work is licensed under the GNU GPL license version 2 or later.
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*
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*/
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#include "qemu/osdep.h"
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#include "qemu/units.h"
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#include "qapi/error.h"
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#include "hw/ppc/ppc.h"
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#include "hw/sysbus.h"
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#include "hw/pci/pci_host.h"
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#include "hw/irq.h"
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#include "hw/or-irq.h"
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#include "hw/pci-host/articia.h"
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#include "hw/pci-host/mv64361.h"
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#include "hw/isa/vt82c686.h"
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#include "hw/ide/pci.h"
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#include "hw/i2c/smbus_eeprom.h"
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#include "hw/qdev-properties.h"
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#include "system/reset.h"
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#include "system/runstate.h"
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#include "system/qtest.h"
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#include "hw/boards.h"
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#include "hw/loader.h"
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#include "hw/fw-path-provider.h"
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#include "elf.h"
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#include "qemu/log.h"
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#include "qemu/error-report.h"
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#include "system/kvm.h"
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#include "kvm_ppc.h"
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#include "system/address-spaces.h"
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#include "qom/qom-qobject.h"
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#include "qobject/qdict.h"
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#include "trace.h"
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#include "qemu/datadir.h"
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#include "system/device_tree.h"
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#include "hw/ppc/vof.h"
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#include <libfdt.h>
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#define PROM_FILENAME "vof.bin"
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#define PROM_ADDR 0xfff00000
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#define PROM_SIZE 0x80000
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#define INITRD_MIN_ADDR 0x600000
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#define KVMPPC_HCALL_BASE 0xf000
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#define KVMPPC_H_RTAS (KVMPPC_HCALL_BASE + 0x0)
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#define KVMPPC_H_VOF_CLIENT (KVMPPC_HCALL_BASE + 0x5)
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#define H_SUCCESS 0
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#define H_PRIVILEGE -3 /* Caller not privileged */
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#define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */
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typedef enum {
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PEGASOS1 = 1,
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PEGASOS2 = 2,
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} PegasosMachineType;
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#define TYPE_PEGASOS_MACHINE MACHINE_TYPE_NAME("pegasos")
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OBJECT_DECLARE_SIMPLE_TYPE(PegasosMachineState, PEGASOS_MACHINE)
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struct PegasosMachineState {
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MachineState parent_obj;
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PegasosMachineType type;
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PowerPCCPU *cpu;
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DeviceState *nb; /* north bridge */
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DeviceState *sb; /* south bridge */
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int bus_freq_hz;
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IRQState pci_irqs[PCI_NUM_PINS];
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OrIRQState orirq[PCI_NUM_PINS];
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qemu_irq mv_pirq[PCI_NUM_PINS];
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qemu_irq via_pirq[PCI_NUM_PINS];
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Vof *vof;
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uint64_t kernel_addr;
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uint64_t kernel_entry;
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uint64_t kernel_size;
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uint64_t initrd_addr;
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uint64_t initrd_size;
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};
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static void *pegasos1_build_fdt(PegasosMachineState *pm, int *fdt_size);
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static void *pegasos2_build_fdt(PegasosMachineState *pm, int *fdt_size);
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static void pegasos_cpu_reset(void *opaque)
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{
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PowerPCCPU *cpu = opaque;
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PegasosMachineState *pm = PEGASOS_MACHINE(current_machine);
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cpu_reset(CPU(cpu));
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cpu->env.spr[SPR_HID1] = 7ULL << 28;
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if (pm->vof) {
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cpu->env.gpr[1] = 2 * VOF_STACK_SIZE - 0x20;
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cpu->env.nip = 0x100;
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} else if (pm->type == PEGASOS1) {
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cpu->env.nip = 0xfffc0100;
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}
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cpu_ppc_tb_reset(&cpu->env);
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}
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static void pegasos2_pci_irq(void *opaque, int n, int level)
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{
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PegasosMachineState *pm = opaque;
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/* PCI interrupt lines are connected to both MV64361 and VT8231 */
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qemu_set_irq(pm->mv_pirq[n], level);
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qemu_set_irq(pm->via_pirq[n], level);
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}
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/* Set up PCI interrupt routing: lines from pci.0 and pci.1 are ORed */
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static void pegasos2_setup_pci_irq(PegasosMachineState *pm)
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{
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for (int h = 0; h < 2; h++) {
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DeviceState *pd;
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g_autofree const char *pn = g_strdup_printf("pcihost%d", h);
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pd = DEVICE(object_resolve_path_component(OBJECT(pm->nb), pn));
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assert(pd);
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for (int i = 0; i < PCI_NUM_PINS; i++) {
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OrIRQState *ori = &pm->orirq[i];
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if (h == 0) {
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g_autofree const char *n = g_strdup_printf("pci-orirq[%d]", i);
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object_initialize_child_with_props(OBJECT(pm), n,
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ori, sizeof(*ori),
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TYPE_OR_IRQ, &error_fatal,
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"num-lines", "2", NULL);
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qdev_realize(DEVICE(ori), NULL, &error_fatal);
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qemu_init_irq(&pm->pci_irqs[i], pegasos2_pci_irq, pm, i);
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qdev_connect_gpio_out(DEVICE(ori), 0, &pm->pci_irqs[i]);
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pm->mv_pirq[i] = qdev_get_gpio_in_named(pm->nb, "gpp", 12 + i);
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pm->via_pirq[i] = qdev_get_gpio_in_named(pm->sb, "pirq", i);
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}
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qdev_connect_gpio_out(pd, i, qdev_get_gpio_in(DEVICE(ori), h));
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}
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}
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qdev_connect_gpio_out_named(pm->sb, "intr", 0,
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qdev_get_gpio_in_named(pm->nb, "gpp", 31));
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}
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static void pegasos_init(MachineState *machine)
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{
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PegasosMachineState *pm = PEGASOS_MACHINE(machine);
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CPUPPCState *env;
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MemoryRegion *rom = g_new(MemoryRegion, 1);
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PCIBus *pci_bus = NULL;
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Object *via;
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PCIDevice *dev;
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I2CBus *i2c_bus;
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const char *fwname = machine->firmware ?: PROM_FILENAME;
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char *filename;
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hwaddr prom_addr;
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ssize_t sz;
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int devfn;
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uint8_t *spd_data;
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/* init CPU */
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pm->cpu = POWERPC_CPU(cpu_create(machine->cpu_type));
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env = &pm->cpu->env;
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if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
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error_report("Incompatible CPU, only 6xx bus supported");
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exit(1);
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}
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/* Set time-base frequency */
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cpu_ppc_tb_init(env, pm->bus_freq_hz / 4);
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qemu_register_reset(pegasos_cpu_reset, pm->cpu);
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/* RAM */
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if (machine->ram_size > 2 * GiB) {
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error_report("RAM size more than 2 GiB is not supported");
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exit(1);
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}
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memory_region_add_subregion(get_system_memory(), 0, machine->ram);
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/* allocate and load firmware */
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filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, fwname);
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if (!filename) {
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error_report("Could not find firmware '%s'", fwname);
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exit(1);
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}
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if (!machine->firmware && !pm->vof) {
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pm->vof = g_malloc0(sizeof(*pm->vof));
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}
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prom_addr = PROM_ADDR;
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if (pm->type == PEGASOS1) {
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prom_addr += PROM_SIZE;
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}
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memory_region_init_rom(rom, NULL, "rom", PROM_SIZE, &error_fatal);
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memory_region_add_subregion(get_system_memory(), prom_addr, rom);
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sz = load_elf(filename, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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ELFDATA2MSB, PPC_ELF_MACHINE, 0, 0);
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if (sz <= 0) {
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sz = load_image_targphys(filename, pm->vof ? 0 : prom_addr, PROM_SIZE,
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&error_fatal);
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}
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if (sz <= 0 || sz > PROM_SIZE) {
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error_report("Could not load firmware '%s'", filename);
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exit(1);
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}
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g_free(filename);
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if (pm->vof) {
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pm->vof->fw_size = sz;
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}
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/* north bridge */
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switch (pm->type) {
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case PEGASOS1:
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{
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MemoryRegion *pci_mem, *mr;
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/* Articia S */
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pm->nb = DEVICE(sysbus_create_simple(TYPE_ARTICIA, 0xfe000000, NULL));
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pci_mem = sysbus_mmio_get_region(SYS_BUS_DEVICE(pm->nb), 1);
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mr = g_new(MemoryRegion, 1);
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memory_region_init_alias(mr, OBJECT(pm->nb), "pci-mem-low", pci_mem,
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0, 0x1000000);
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memory_region_add_subregion(get_system_memory(), 0xfd000000, mr);
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mr = g_new(MemoryRegion, 1);
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memory_region_init_alias(mr, OBJECT(pm->nb), "pci-mem-high", pci_mem,
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0x80000000, 0x7d000000);
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memory_region_add_subregion(get_system_memory(), 0x80000000, mr);
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pci_bus = PCI_BUS(qdev_get_child_bus(pm->nb, "pci.0"));
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break;
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}
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case PEGASOS2:
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/* Marvell Discovery II system controller */
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pm->nb = DEVICE(sysbus_create_simple(TYPE_MV64361, -1,
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qdev_get_gpio_in(DEVICE(pm->cpu), PPC6xx_INPUT_INT)));
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pci_bus = mv64361_get_pci_bus(pm->nb, 1);
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break;
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}
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/* VIA VT8231 South Bridge (multifunction PCI device) */
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devfn = PCI_DEVFN(pm->type == PEGASOS1 ? 7 : 12, 0);
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pm->sb = DEVICE(pci_new_multifunction(devfn, TYPE_VT8231_ISA));
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via = OBJECT(pm->sb);
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/* Set properties on individual devices before realizing the south bridge */
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if (machine->audiodev) {
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dev = PCI_DEVICE(object_resolve_path_component(via, "ac97"));
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qdev_prop_set_string(DEVICE(dev), "audiodev", machine->audiodev);
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}
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pci_realize_and_unref(PCI_DEVICE(via), pci_bus, &error_abort);
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object_property_add_alias(OBJECT(machine), "rtc-time",
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object_resolve_path_component(via, "rtc"),
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"date");
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dev = PCI_DEVICE(object_resolve_path_component(via, "ide"));
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pci_ide_create_devs(dev);
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dev = PCI_DEVICE(object_resolve_path_component(via, "pm"));
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i2c_bus = I2C_BUS(qdev_get_child_bus(DEVICE(dev), "i2c"));
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spd_data = spd_data_generate(DDR, machine->ram_size);
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smbus_eeprom_init_one(i2c_bus, 0x57, spd_data);
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/* other PC hardware */
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pci_vga_init(pci_bus);
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/* pci interrupt routing */
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switch (pm->type) {
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case PEGASOS1:
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qdev_connect_gpio_out_named(pm->sb, "intr", 0,
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qdev_get_gpio_in(DEVICE(pm->cpu),
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PPC6xx_INPUT_INT));
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for (int i = 0; i < PCI_NUM_PINS; i++) {
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qdev_connect_gpio_out(pm->nb, i,
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qdev_get_gpio_in_named(pm->sb, "pirq", i));
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}
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break;
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case PEGASOS2:
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pegasos2_setup_pci_irq(pm);
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break;
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}
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if (machine->kernel_filename) {
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sz = load_elf(machine->kernel_filename, NULL, NULL, NULL,
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&pm->kernel_entry, &pm->kernel_addr, NULL, NULL,
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ELFDATA2MSB, PPC_ELF_MACHINE, 0, 0);
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if (sz <= 0) {
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error_report("Could not load kernel '%s'",
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machine->kernel_filename);
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exit(1);
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}
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pm->kernel_size = sz;
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if (!pm->vof) {
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warn_report("Option -kernel may be ineffective with -bios.");
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}
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} else if (pm->vof && !qtest_enabled()) {
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warn_report("Using Virtual OpenFirmware but no -kernel option.");
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}
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if (machine->initrd_filename) {
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pm->initrd_addr = pm->kernel_addr + pm->kernel_size + 64 * KiB;
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pm->initrd_addr = ROUND_UP(pm->initrd_addr, 4);
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pm->initrd_addr = MAX(pm->initrd_addr, INITRD_MIN_ADDR);
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sz = load_image_targphys(machine->initrd_filename, pm->initrd_addr,
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machine->ram_size - pm->initrd_addr, &error_fatal);
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pm->initrd_size = sz;
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}
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if (!pm->vof && machine->kernel_cmdline && machine->kernel_cmdline[0]) {
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warn_report("Option -append may be ineffective with -bios.");
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}
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}
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static void pegasos_superio_write(uint8_t addr, uint8_t val)
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{
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cpu_physical_memory_write(0xfe0003f0, &addr, 1);
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cpu_physical_memory_write(0xfe0003f1, &val, 1);
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}
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static void pegasos1_pci_config_write(PegasosMachineState *pm, int bus,
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uint32_t addr, uint32_t len, uint32_t val)
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{
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addr |= BIT(31);
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cpu_physical_memory_write(0xfec00cf8, &addr, 4);
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cpu_physical_memory_write(0xfee00cfc, &val, len);
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}
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static void pegasos1_chipset_reset(PegasosMachineState *pm)
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{
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uint8_t elcr = 0x2e;
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cpu_physical_memory_write(0xfe0004d1, &elcr, sizeof(elcr));
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pegasos1_pci_config_write(pm, 0, PCI_COMMAND, 2, PCI_COMMAND_IO |
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PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
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pegasos1_pci_config_write(pm, 0, (PCI_DEVFN(7, 0) << 8) |
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PCI_INTERRUPT_LINE, 2, 0x9);
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pegasos1_pci_config_write(pm, 0, (PCI_DEVFN(7, 0) << 8) |
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0x50, 1, 0x6);
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pegasos_superio_write(0xf4, 0xbe);
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pegasos_superio_write(0xf6, 0xef);
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pegasos_superio_write(0xf7, 0xfc);
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pegasos_superio_write(0xf2, 0x14);
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pegasos1_pci_config_write(pm, 0, (PCI_DEVFN(7, 0) << 8) |
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0x51, 1, 0x3d);
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pegasos1_pci_config_write(pm, 0, (PCI_DEVFN(7, 0) << 8) |
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0x55, 1, 0x90);
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pegasos1_pci_config_write(pm, 0, (PCI_DEVFN(7, 0) << 8) |
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0x56, 1, 0x99);
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pegasos1_pci_config_write(pm, 0, (PCI_DEVFN(7, 0) << 8) |
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0x57, 1, 0x90);
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pegasos1_pci_config_write(pm, 0, (PCI_DEVFN(7, 1) << 8) |
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PCI_INTERRUPT_LINE, 2, 0x10e);
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pegasos1_pci_config_write(pm, 0, (PCI_DEVFN(7, 1) << 8) |
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PCI_CLASS_PROG, 1, 0xf);
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pegasos1_pci_config_write(pm, 0, (PCI_DEVFN(7, 1) << 8) |
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0x40, 1, 0xb);
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pegasos1_pci_config_write(pm, 0, (PCI_DEVFN(7, 1) << 8) |
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0x50, 4, 0x17171717);
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pegasos1_pci_config_write(pm, 0, (PCI_DEVFN(7, 1) << 8) |
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PCI_COMMAND, 2, 0x87);
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pegasos1_pci_config_write(pm, 0, (PCI_DEVFN(7, 2) << 8) |
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PCI_INTERRUPT_LINE, 2, 0x409);
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pegasos1_pci_config_write(pm, 0, (PCI_DEVFN(7, 2) << 8) |
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PCI_COMMAND, 2, 0x7);
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pegasos1_pci_config_write(pm, 0, (PCI_DEVFN(7, 3) << 8) |
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PCI_INTERRUPT_LINE, 2, 0x409);
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pegasos1_pci_config_write(pm, 0, (PCI_DEVFN(7, 3) << 8) |
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PCI_COMMAND, 2, 0x7);
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pegasos1_pci_config_write(pm, 0, (PCI_DEVFN(7, 4) << 8) |
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PCI_INTERRUPT_LINE, 2, 0x9);
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pegasos1_pci_config_write(pm, 0, (PCI_DEVFN(7, 4) << 8) |
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0x48, 4, 0x2001);
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pegasos1_pci_config_write(pm, 0, (PCI_DEVFN(7, 4) << 8) |
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0x41, 1, 0);
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pegasos1_pci_config_write(pm, 0, (PCI_DEVFN(7, 4) << 8) |
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0x90, 4, 0x1000);
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pegasos1_pci_config_write(pm, 0, (PCI_DEVFN(7, 5) << 8) |
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PCI_INTERRUPT_LINE, 2, 0x309);
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pegasos1_pci_config_write(pm, 0, (PCI_DEVFN(7, 6) << 8) |
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PCI_INTERRUPT_LINE, 2, 0x309);
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}
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static uint32_t pegasos2_mv_reg_read(PegasosMachineState *pm,
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uint32_t addr, uint32_t len)
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{
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MemoryRegion *r = sysbus_mmio_get_region(SYS_BUS_DEVICE(pm->nb), 0);
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uint64_t val = 0xffffffffULL;
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memory_region_dispatch_read(r, addr, &val, size_memop(len) | MO_LE,
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MEMTXATTRS_UNSPECIFIED);
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return val;
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}
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static void pegasos2_mv_reg_write(PegasosMachineState *pm, uint32_t addr,
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uint32_t len, uint32_t val)
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{
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MemoryRegion *r = sysbus_mmio_get_region(SYS_BUS_DEVICE(pm->nb), 0);
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memory_region_dispatch_write(r, addr, val, size_memop(len) | MO_LE,
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MEMTXATTRS_UNSPECIFIED);
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}
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#define PCI0_CFG_ADDR 0xcf8
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#define PCI1_CFG_ADDR 0xc78
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static uint32_t pegasos2_pci_config_read(PegasosMachineState *pm, int bus,
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uint32_t addr, uint32_t len)
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{
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hwaddr pcicfg = bus ? PCI1_CFG_ADDR : PCI0_CFG_ADDR;
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uint64_t val = 0xffffffffULL;
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if (len <= 4) {
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pegasos2_mv_reg_write(pm, pcicfg, 4, addr | BIT(31));
|
|
val = pegasos2_mv_reg_read(pm, pcicfg + 4, len);
|
|
}
|
|
return val;
|
|
}
|
|
|
|
static void pegasos2_pci_config_write(PegasosMachineState *pm, int bus,
|
|
uint32_t addr, uint32_t len, uint32_t val)
|
|
{
|
|
hwaddr pcicfg = bus ? PCI1_CFG_ADDR : PCI0_CFG_ADDR;
|
|
|
|
pegasos2_mv_reg_write(pm, pcicfg, 4, addr | BIT(31));
|
|
pegasos2_mv_reg_write(pm, pcicfg + 4, len, val);
|
|
}
|
|
|
|
static void pegasos2_chipset_reset(PegasosMachineState *pm)
|
|
{
|
|
pegasos2_mv_reg_write(pm, 0, 4, 0x28020ff);
|
|
pegasos2_mv_reg_write(pm, 0x278, 4, 0xa31fc);
|
|
pegasos2_mv_reg_write(pm, 0xf300, 4, 0x11ff0400);
|
|
pegasos2_mv_reg_write(pm, 0xf10c, 4, 0x80000000);
|
|
pegasos2_mv_reg_write(pm, 0x1c, 4, 0x8000000);
|
|
pegasos2_pci_config_write(pm, 0, PCI_COMMAND, 2, PCI_COMMAND_IO |
|
|
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
|
|
pegasos2_pci_config_write(pm, 1, PCI_COMMAND, 2, PCI_COMMAND_IO |
|
|
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
|
|
|
|
pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 0) << 8) |
|
|
PCI_INTERRUPT_LINE, 2, 0x9);
|
|
pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 0) << 8) |
|
|
0x50, 1, 0x6);
|
|
pegasos_superio_write(0xf4, 0xbe);
|
|
pegasos_superio_write(0xf6, 0xef);
|
|
pegasos_superio_write(0xf7, 0xfc);
|
|
pegasos_superio_write(0xf2, 0x14);
|
|
pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 0) << 8) |
|
|
0x50, 1, 0x2);
|
|
pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 0) << 8) |
|
|
0x55, 1, 0x90);
|
|
pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 0) << 8) |
|
|
0x56, 1, 0x99);
|
|
pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 0) << 8) |
|
|
0x57, 1, 0x90);
|
|
|
|
pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 1) << 8) |
|
|
PCI_INTERRUPT_LINE, 2, 0x109);
|
|
pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 1) << 8) |
|
|
PCI_CLASS_PROG, 1, 0xf);
|
|
pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 1) << 8) |
|
|
0x40, 1, 0xb);
|
|
pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 1) << 8) |
|
|
0x50, 4, 0x17171717);
|
|
pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 1) << 8) |
|
|
PCI_COMMAND, 2, 0x87);
|
|
|
|
pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 2) << 8) |
|
|
PCI_INTERRUPT_LINE, 2, 0x409);
|
|
pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 2) << 8) |
|
|
PCI_COMMAND, 2, 0x7);
|
|
|
|
pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 3) << 8) |
|
|
PCI_INTERRUPT_LINE, 2, 0x409);
|
|
pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 3) << 8) |
|
|
PCI_COMMAND, 2, 0x7);
|
|
|
|
pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 4) << 8) |
|
|
PCI_INTERRUPT_LINE, 2, 0x9);
|
|
pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 4) << 8) |
|
|
0x48, 4, 0xf00);
|
|
pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 4) << 8) |
|
|
0x40, 4, 0x558020);
|
|
pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 4) << 8) |
|
|
0x90, 4, 0xd00);
|
|
|
|
pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 5) << 8) |
|
|
PCI_INTERRUPT_LINE, 2, 0x309);
|
|
|
|
pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 6) << 8) |
|
|
PCI_INTERRUPT_LINE, 2, 0x309);
|
|
}
|
|
|
|
static void pegasos_machine_reset(MachineState *machine, ResetType type)
|
|
{
|
|
PegasosMachineState *pm = PEGASOS_MACHINE(machine);
|
|
void *fdt = NULL;
|
|
uint32_t c[2];
|
|
uint64_t d[2];
|
|
int sz;
|
|
|
|
qemu_devices_reset(type);
|
|
if (!pm->vof) {
|
|
return; /* Firmware should set up machine so nothing to do */
|
|
}
|
|
|
|
/* Otherwise, set up devices that board firmware would normally do */
|
|
switch (pm->type) {
|
|
case PEGASOS1:
|
|
pegasos1_chipset_reset(pm);
|
|
fdt = pegasos1_build_fdt(pm, &sz);
|
|
break;
|
|
case PEGASOS2:
|
|
pegasos2_chipset_reset(pm);
|
|
fdt = pegasos2_build_fdt(pm, &sz);
|
|
break;
|
|
}
|
|
if (!fdt) {
|
|
exit(1);
|
|
}
|
|
|
|
/* Device tree and VOF set up */
|
|
vof_init(pm->vof, machine->ram_size, &error_fatal);
|
|
if (vof_claim(pm->vof, 0, VOF_STACK_SIZE, VOF_STACK_SIZE) == -1) {
|
|
error_report("Memory allocation for stack failed");
|
|
exit(1);
|
|
}
|
|
if (pm->kernel_size &&
|
|
vof_claim(pm->vof, pm->kernel_addr, pm->kernel_size, 0) == -1) {
|
|
error_report("Memory for kernel is in use");
|
|
exit(1);
|
|
}
|
|
if (pm->initrd_size &&
|
|
vof_claim(pm->vof, pm->initrd_addr, pm->initrd_size, 0) == -1) {
|
|
error_report("Memory for initrd is in use");
|
|
exit(1);
|
|
}
|
|
|
|
/* Set memory size */
|
|
c[0] = 0;
|
|
c[1] = cpu_to_be32(machine->ram_size);
|
|
qemu_fdt_setprop(fdt, "/memory@0", "reg", c, sizeof(c));
|
|
|
|
/* Boot parameters */
|
|
if (pm->initrd_addr && pm->initrd_size) {
|
|
qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
|
|
pm->initrd_addr + pm->initrd_size);
|
|
qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start",
|
|
pm->initrd_addr);
|
|
}
|
|
qemu_fdt_setprop_string(fdt, "/chosen", "bootargs",
|
|
machine->kernel_cmdline ?: "");
|
|
/* FIXME: VOF assumes entry is same as load address */
|
|
d[0] = cpu_to_be64(pm->kernel_entry);
|
|
d[1] = cpu_to_be64(pm->kernel_size - (pm->kernel_entry - pm->kernel_addr));
|
|
qemu_fdt_setprop(fdt, "/chosen", "qemu,boot-kernel", d, sizeof(d));
|
|
|
|
vof_build_dt(fdt, pm->vof);
|
|
vof_client_open_store(fdt, pm->vof, "/chosen", "stdin", "/failsafe");
|
|
vof_client_open_store(fdt, pm->vof, "/chosen", "stdout", "/failsafe");
|
|
|
|
/* Set machine->fdt for 'dumpdtb' QMP/HMP command */
|
|
g_free(machine->fdt);
|
|
machine->fdt = fdt;
|
|
|
|
pm->cpu->vhyp = PPC_VIRTUAL_HYPERVISOR(machine);
|
|
pm->cpu->vhyp_class = PPC_VIRTUAL_HYPERVISOR_GET_CLASS(pm->cpu->vhyp);
|
|
}
|
|
|
|
enum pegasos2_rtas_tokens {
|
|
RTAS_RESTART_RTAS = 0,
|
|
RTAS_NVRAM_FETCH = 1,
|
|
RTAS_NVRAM_STORE = 2,
|
|
RTAS_GET_TIME_OF_DAY = 3,
|
|
RTAS_SET_TIME_OF_DAY = 4,
|
|
RTAS_EVENT_SCAN = 6,
|
|
RTAS_CHECK_EXCEPTION = 7,
|
|
RTAS_READ_PCI_CONFIG = 8,
|
|
RTAS_WRITE_PCI_CONFIG = 9,
|
|
RTAS_DISPLAY_CHARACTER = 10,
|
|
RTAS_SET_INDICATOR = 11,
|
|
RTAS_POWER_OFF = 17,
|
|
RTAS_SUSPEND = 18,
|
|
RTAS_HIBERNATE = 19,
|
|
RTAS_SYSTEM_REBOOT = 20,
|
|
};
|
|
|
|
static target_ulong pegasos2_rtas(PowerPCCPU *cpu, PegasosMachineState *pm,
|
|
target_ulong args_real)
|
|
{
|
|
AddressSpace *as = CPU(cpu)->as;
|
|
uint32_t token = ldl_be_phys(as, args_real);
|
|
uint32_t nargs = ldl_be_phys(as, args_real + 4);
|
|
uint32_t nrets = ldl_be_phys(as, args_real + 8);
|
|
uint32_t args = args_real + 12;
|
|
uint32_t rets = args_real + 12 + nargs * 4;
|
|
|
|
if (nrets < 1) {
|
|
qemu_log_mask(LOG_GUEST_ERROR, "Too few return values in RTAS call\n");
|
|
return H_PARAMETER;
|
|
}
|
|
switch (token) {
|
|
case RTAS_GET_TIME_OF_DAY:
|
|
{
|
|
QObject *qo = object_property_get_qobject(qdev_get_machine(),
|
|
"rtc-time", &error_fatal);
|
|
QDict *qd = qobject_to(QDict, qo);
|
|
|
|
if (nargs != 0 || nrets != 8 || !qd) {
|
|
stl_be_phys(as, rets, -1);
|
|
qobject_unref(qo);
|
|
return H_PARAMETER;
|
|
}
|
|
|
|
stl_be_phys(as, rets, 0);
|
|
stl_be_phys(as, rets + 4, qdict_get_int(qd, "tm_year") + 1900);
|
|
stl_be_phys(as, rets + 8, qdict_get_int(qd, "tm_mon") + 1);
|
|
stl_be_phys(as, rets + 12, qdict_get_int(qd, "tm_mday"));
|
|
stl_be_phys(as, rets + 16, qdict_get_int(qd, "tm_hour"));
|
|
stl_be_phys(as, rets + 20, qdict_get_int(qd, "tm_min"));
|
|
stl_be_phys(as, rets + 24, qdict_get_int(qd, "tm_sec"));
|
|
stl_be_phys(as, rets + 28, 0);
|
|
qobject_unref(qo);
|
|
return H_SUCCESS;
|
|
}
|
|
case RTAS_READ_PCI_CONFIG:
|
|
{
|
|
uint32_t addr, len, val;
|
|
|
|
if (nargs != 2 || nrets != 2) {
|
|
stl_be_phys(as, rets, -1);
|
|
return H_PARAMETER;
|
|
}
|
|
addr = ldl_be_phys(as, args);
|
|
len = ldl_be_phys(as, args + 4);
|
|
val = pegasos2_pci_config_read(pm, !(addr >> 24),
|
|
addr & 0x0fffffff, len);
|
|
stl_be_phys(as, rets, 0);
|
|
stl_be_phys(as, rets + 4, val);
|
|
return H_SUCCESS;
|
|
}
|
|
case RTAS_WRITE_PCI_CONFIG:
|
|
{
|
|
uint32_t addr, len, val;
|
|
|
|
if (nargs != 3 || nrets != 1) {
|
|
stl_be_phys(as, rets, -1);
|
|
return H_PARAMETER;
|
|
}
|
|
addr = ldl_be_phys(as, args);
|
|
len = ldl_be_phys(as, args + 4);
|
|
val = ldl_be_phys(as, args + 8);
|
|
pegasos2_pci_config_write(pm, !(addr >> 24),
|
|
addr & 0x0fffffff, len, val);
|
|
stl_be_phys(as, rets, 0);
|
|
return H_SUCCESS;
|
|
}
|
|
case RTAS_DISPLAY_CHARACTER:
|
|
if (nargs != 1 || nrets != 1) {
|
|
stl_be_phys(as, rets, -1);
|
|
return H_PARAMETER;
|
|
}
|
|
qemu_log_mask(LOG_UNIMP, "%c", ldl_be_phys(as, args));
|
|
stl_be_phys(as, rets, 0);
|
|
return H_SUCCESS;
|
|
case RTAS_POWER_OFF:
|
|
{
|
|
if (nargs != 2 || nrets != 1) {
|
|
stl_be_phys(as, rets, -1);
|
|
return H_PARAMETER;
|
|
}
|
|
qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
|
|
stl_be_phys(as, rets, 0);
|
|
return H_SUCCESS;
|
|
}
|
|
default:
|
|
qemu_log_mask(LOG_UNIMP, "Unknown RTAS token %u (args=%u, rets=%u)\n",
|
|
token, nargs, nrets);
|
|
stl_be_phys(as, rets, 0);
|
|
return H_SUCCESS;
|
|
}
|
|
}
|
|
|
|
static bool pegasos_cpu_in_nested(PowerPCCPU *cpu)
|
|
{
|
|
return false;
|
|
}
|
|
|
|
static void pegasos_hypercall(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu)
|
|
{
|
|
PegasosMachineState *pm = PEGASOS_MACHINE(vhyp);
|
|
CPUPPCState *env = &cpu->env;
|
|
|
|
/* The TCG path should also be holding the BQL at this point */
|
|
g_assert(bql_locked());
|
|
|
|
if (FIELD_EX64(env->msr, MSR, PR)) {
|
|
qemu_log_mask(LOG_GUEST_ERROR, "Hypercall made with MSR[PR]=1\n");
|
|
env->gpr[3] = H_PRIVILEGE;
|
|
} else if (env->gpr[3] == KVMPPC_H_RTAS && pm->type == PEGASOS2) {
|
|
env->gpr[3] = pegasos2_rtas(cpu, pm, env->gpr[4]);
|
|
} else if (env->gpr[3] == KVMPPC_H_VOF_CLIENT) {
|
|
int ret = vof_client_call(MACHINE(pm), pm->vof, MACHINE(pm)->fdt,
|
|
env->gpr[4]);
|
|
env->gpr[3] = (ret ? H_PARAMETER : H_SUCCESS);
|
|
} else {
|
|
qemu_log_mask(LOG_GUEST_ERROR, "Unsupported hypercall " TARGET_FMT_lx
|
|
"\n", env->gpr[3]);
|
|
env->gpr[3] = -1;
|
|
}
|
|
}
|
|
|
|
static void vhyp_nop(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu)
|
|
{
|
|
}
|
|
|
|
static target_ulong vhyp_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp)
|
|
{
|
|
return POWERPC_CPU(current_cpu)->env.spr[SPR_SDR1];
|
|
}
|
|
|
|
static bool pegasos_setprop(MachineState *ms, const char *path,
|
|
const char *propname, void *val, int vallen)
|
|
{
|
|
return true;
|
|
}
|
|
|
|
static void pegasos_machine_init(MachineClass *mc)
|
|
{
|
|
PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(mc);
|
|
VofMachineIfClass *vmc = VOF_MACHINE_CLASS(mc);
|
|
|
|
mc->init = pegasos_init;
|
|
mc->reset = pegasos_machine_reset;
|
|
mc->block_default_type = IF_IDE;
|
|
mc->default_boot_order = "cd";
|
|
mc->default_display = "std";
|
|
mc->default_ram_id = "ram";
|
|
mc->default_ram_size = 512 * MiB;
|
|
machine_add_audiodev_property(mc);
|
|
|
|
vhc->cpu_in_nested = pegasos_cpu_in_nested;
|
|
vhc->hypercall = pegasos_hypercall;
|
|
vhc->cpu_exec_enter = vhyp_nop;
|
|
vhc->cpu_exec_exit = vhyp_nop;
|
|
vhc->encode_hpt_for_kvm_pr = vhyp_encode_hpt_for_kvm_pr;
|
|
|
|
vmc->setprop = pegasos_setprop;
|
|
}
|
|
|
|
static void pegasos1_init(Object *obj)
|
|
{
|
|
PegasosMachineState *pm = PEGASOS_MACHINE(obj);
|
|
|
|
pm->type = PEGASOS1;
|
|
pm->bus_freq_hz = 33000000;
|
|
}
|
|
|
|
static void pegasos1_machine_class_init(ObjectClass *oc, const void *data)
|
|
{
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
|
|
mc->desc = "Genesi/bPlan Pegasos I";
|
|
mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("750cxe_v3.1b");
|
|
}
|
|
|
|
static void pegasos2_init(Object *obj)
|
|
{
|
|
PegasosMachineState *pm = PEGASOS_MACHINE(obj);
|
|
|
|
pm->type = PEGASOS2;
|
|
pm->bus_freq_hz = 133333333;
|
|
}
|
|
|
|
static void pegasos2_machine_class_init(ObjectClass *oc, const void *data)
|
|
{
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
|
|
mc->desc = "Genesi/bPlan Pegasos II";
|
|
mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("7457_v1.2");
|
|
}
|
|
|
|
DEFINE_MACHINE_EXTENDED("pegasos", MACHINE, PegasosMachineState,
|
|
pegasos_machine_init, true, (const InterfaceInfo[]) {
|
|
{ TYPE_PPC_VIRTUAL_HYPERVISOR },
|
|
{ TYPE_VOF_MACHINE_IF }, { } })
|
|
|
|
static const TypeInfo pegasos_machine_types[] = {
|
|
{
|
|
.name = MACHINE_TYPE_NAME("pegasos1"),
|
|
.parent = TYPE_PEGASOS_MACHINE,
|
|
.class_init = pegasos1_machine_class_init,
|
|
.instance_init = pegasos1_init,
|
|
},
|
|
{
|
|
.name = MACHINE_TYPE_NAME("pegasos2"),
|
|
.parent = TYPE_PEGASOS_MACHINE,
|
|
.class_init = pegasos2_machine_class_init,
|
|
.instance_init = pegasos2_init,
|
|
},
|
|
};
|
|
|
|
DEFINE_TYPES(pegasos_machine_types)
|
|
|
|
/* FDT creation for passing to firmware */
|
|
|
|
typedef struct {
|
|
void *fdt;
|
|
const char *path;
|
|
} FDTInfo;
|
|
|
|
/* We do everything in reverse order so it comes out right in the tree */
|
|
|
|
static void dt_ide(PCIBus *bus, PCIDevice *d, FDTInfo *fi)
|
|
{
|
|
qemu_fdt_setprop_string(fi->fdt, fi->path, "device_type", "spi");
|
|
}
|
|
|
|
static void dt_usb(PCIBus *bus, PCIDevice *d, FDTInfo *fi)
|
|
{
|
|
qemu_fdt_setprop_cell(fi->fdt, fi->path, "#size-cells", 0);
|
|
qemu_fdt_setprop_cell(fi->fdt, fi->path, "#address-cells", 1);
|
|
qemu_fdt_setprop_string(fi->fdt, fi->path, "device_type", "usb");
|
|
}
|
|
|
|
static struct {
|
|
const char *id;
|
|
const char *name;
|
|
void (*dtf)(PCIBus *bus, PCIDevice *d, FDTInfo *fi);
|
|
} device_map[] = {
|
|
{ "pci10cc,660", "host", NULL },
|
|
{ "pci10cc,661", "host", NULL },
|
|
{ "pci11ab,6460", "host", NULL },
|
|
{ "pci1106,571", "ide", dt_ide },
|
|
{ "pci1106,3044", "firewire", NULL },
|
|
{ "pci1106,3038", "usb", dt_usb },
|
|
{ "pci1106,8235", "other", NULL },
|
|
{ "pci1106,3058", "sound", NULL },
|
|
{ NULL, NULL }
|
|
};
|
|
|
|
static void add_pci_device(PCIBus *bus, PCIDevice *d, void *opaque)
|
|
{
|
|
FDTInfo *fi = opaque;
|
|
GString *node;
|
|
uint32_t cells[(PCI_NUM_REGIONS + 1) * 5];
|
|
int i, j;
|
|
const char *name = NULL;
|
|
g_autofree const gchar *pn = g_strdup_printf("pci%x,%x",
|
|
pci_get_word(&d->config[PCI_VENDOR_ID]),
|
|
pci_get_word(&d->config[PCI_DEVICE_ID]));
|
|
|
|
if (!strcmp(pn, "pci1106,8231")) {
|
|
return; /* ISA bridge and devices are included in dtb */
|
|
}
|
|
if (pci_get_word(&d->config[PCI_CLASS_DEVICE]) ==
|
|
PCI_CLASS_NETWORK_ETHERNET) {
|
|
name = "ethernet";
|
|
} else if (pci_get_word(&d->config[PCI_CLASS_DEVICE]) >> 8 ==
|
|
PCI_BASE_CLASS_DISPLAY) {
|
|
name = "display";
|
|
}
|
|
for (i = 0; device_map[i].id; i++) {
|
|
if (!strcmp(pn, device_map[i].id)) {
|
|
name = device_map[i].name;
|
|
break;
|
|
}
|
|
}
|
|
node = g_string_new(NULL);
|
|
g_string_printf(node, "%s/%s@%x", fi->path, (name ?: pn),
|
|
PCI_SLOT(d->devfn));
|
|
if (PCI_FUNC(d->devfn)) {
|
|
g_string_append_printf(node, ",%x", PCI_FUNC(d->devfn));
|
|
}
|
|
|
|
qemu_fdt_add_subnode(fi->fdt, node->str);
|
|
if (device_map[i].dtf) {
|
|
FDTInfo cfi = { fi->fdt, node->str };
|
|
device_map[i].dtf(bus, d, &cfi);
|
|
}
|
|
cells[0] = cpu_to_be32(d->devfn << 8);
|
|
cells[1] = 0;
|
|
cells[2] = 0;
|
|
cells[3] = 0;
|
|
cells[4] = 0;
|
|
j = 5;
|
|
for (i = 0; i < PCI_NUM_REGIONS; i++) {
|
|
if (!d->io_regions[i].size) {
|
|
continue;
|
|
}
|
|
cells[j] = PCI_BASE_ADDRESS_0 + i * 4;
|
|
if (cells[j] == 0x28) {
|
|
cells[j] = 0x30;
|
|
}
|
|
cells[j] = cpu_to_be32(d->devfn << 8 | cells[j]);
|
|
if (d->io_regions[i].type & PCI_BASE_ADDRESS_SPACE_IO) {
|
|
cells[j] |= cpu_to_be32(1 << 24);
|
|
} else {
|
|
if (d->io_regions[i].type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
|
|
cells[j] |= cpu_to_be32(3 << 24);
|
|
} else {
|
|
cells[j] |= cpu_to_be32(2 << 24);
|
|
}
|
|
if (d->io_regions[i].type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
|
|
cells[j] |= cpu_to_be32(4 << 28);
|
|
}
|
|
}
|
|
cells[j + 1] = 0;
|
|
cells[j + 2] = 0;
|
|
cells[j + 3] = cpu_to_be32(d->io_regions[i].size >> 32);
|
|
cells[j + 4] = cpu_to_be32(d->io_regions[i].size);
|
|
j += 5;
|
|
}
|
|
qemu_fdt_setprop(fi->fdt, node->str, "reg", cells, j * sizeof(cells[0]));
|
|
if (pci_get_byte(&d->config[PCI_INTERRUPT_PIN])) {
|
|
qemu_fdt_setprop_cell(fi->fdt, node->str, "interrupts",
|
|
pci_get_byte(&d->config[PCI_INTERRUPT_PIN]));
|
|
}
|
|
/* Pegasos firmware has subsystem-id and subsystem-vendor-id swapped */
|
|
qemu_fdt_setprop_cell(fi->fdt, node->str, "subsystem-vendor-id",
|
|
pci_get_word(&d->config[PCI_SUBSYSTEM_ID]));
|
|
qemu_fdt_setprop_cell(fi->fdt, node->str, "subsystem-id",
|
|
pci_get_word(&d->config[PCI_SUBSYSTEM_VENDOR_ID]));
|
|
cells[0] = pci_get_long(&d->config[PCI_CLASS_REVISION]);
|
|
qemu_fdt_setprop_cell(fi->fdt, node->str, "class-code", cells[0] >> 8);
|
|
qemu_fdt_setprop_cell(fi->fdt, node->str, "revision-id", cells[0] & 0xff);
|
|
qemu_fdt_setprop_cell(fi->fdt, node->str, "device-id",
|
|
pci_get_word(&d->config[PCI_DEVICE_ID]));
|
|
qemu_fdt_setprop_cell(fi->fdt, node->str, "vendor-id",
|
|
pci_get_word(&d->config[PCI_VENDOR_ID]));
|
|
|
|
g_string_free(node, TRUE);
|
|
}
|
|
|
|
static void add_cpu_info(void *fdt, PowerPCCPU *cpu, int bus_freq)
|
|
{
|
|
uint32_t cells[2];
|
|
|
|
/* FIXME Get CPU name from CPU object */
|
|
const char *cp = "/cpus/PowerPC,G4";
|
|
qemu_fdt_add_subnode(fdt, cp);
|
|
qemu_fdt_setprop_cell(fdt, cp, "l2cr", 0);
|
|
qemu_fdt_setprop_cell(fdt, cp, "d-cache-size", 0x8000);
|
|
qemu_fdt_setprop_cell(fdt, cp, "d-cache-block-size",
|
|
cpu->env.dcache_line_size);
|
|
qemu_fdt_setprop_cell(fdt, cp, "d-cache-line-size",
|
|
cpu->env.dcache_line_size);
|
|
qemu_fdt_setprop_cell(fdt, cp, "i-cache-size", 0x8000);
|
|
qemu_fdt_setprop_cell(fdt, cp, "i-cache-block-size",
|
|
cpu->env.icache_line_size);
|
|
qemu_fdt_setprop_cell(fdt, cp, "i-cache-line-size",
|
|
cpu->env.icache_line_size);
|
|
if (ppc_is_split_tlb(cpu)) {
|
|
qemu_fdt_setprop_cell(fdt, cp, "i-tlb-sets", cpu->env.nb_ways);
|
|
qemu_fdt_setprop_cell(fdt, cp, "i-tlb-size", cpu->env.tlb_per_way);
|
|
qemu_fdt_setprop_cell(fdt, cp, "d-tlb-sets", cpu->env.nb_ways);
|
|
qemu_fdt_setprop_cell(fdt, cp, "d-tlb-size", cpu->env.tlb_per_way);
|
|
qemu_fdt_setprop_string(fdt, cp, "tlb-split", "");
|
|
}
|
|
qemu_fdt_setprop_cell(fdt, cp, "tlb-sets", cpu->env.nb_ways);
|
|
qemu_fdt_setprop_cell(fdt, cp, "tlb-size", cpu->env.nb_tlb);
|
|
qemu_fdt_setprop_string(fdt, cp, "state", "running");
|
|
if (cpu->env.insns_flags & PPC_ALTIVEC) {
|
|
qemu_fdt_setprop_string(fdt, cp, "altivec", "");
|
|
qemu_fdt_setprop_string(fdt, cp, "data-streams", "");
|
|
}
|
|
/*
|
|
* FIXME What flags do data-streams, external-control and
|
|
* performance-monitor depend on?
|
|
*/
|
|
qemu_fdt_setprop_string(fdt, cp, "external-control", "");
|
|
if (cpu->env.insns_flags & PPC_FLOAT_FSQRT) {
|
|
qemu_fdt_setprop_string(fdt, cp, "general-purpose", "");
|
|
}
|
|
qemu_fdt_setprop_string(fdt, cp, "performance-monitor", "");
|
|
if (cpu->env.insns_flags & PPC_FLOAT_FRES) {
|
|
qemu_fdt_setprop_string(fdt, cp, "graphics", "");
|
|
}
|
|
qemu_fdt_setprop_cell(fdt, cp, "reservation-granule-size", 4);
|
|
qemu_fdt_setprop_cell(fdt, cp, "timebase-frequency",
|
|
cpu->env.tb_env->tb_freq);
|
|
qemu_fdt_setprop_cell(fdt, cp, "bus-frequency", bus_freq);
|
|
qemu_fdt_setprop_cell(fdt, cp, "clock-frequency", bus_freq * 7.5);
|
|
qemu_fdt_setprop_cell(fdt, cp, "cpu-version", cpu->env.spr[SPR_PVR]);
|
|
cells[0] = 0;
|
|
cells[1] = 0;
|
|
qemu_fdt_setprop(fdt, cp, "reg", cells, 2 * sizeof(cells[0]));
|
|
qemu_fdt_setprop_string(fdt, cp, "device_type", "cpu");
|
|
}
|
|
|
|
static void *load_dtb(const char *filename, int *fdt_size)
|
|
{
|
|
void *fdt;
|
|
g_autofree char *name = qemu_find_file(QEMU_FILE_TYPE_DTB, filename);
|
|
|
|
if (!name) {
|
|
error_report("Could not find dtb file '%s'", filename);
|
|
return NULL;
|
|
}
|
|
fdt = load_device_tree(name, fdt_size);
|
|
if (!fdt) {
|
|
error_report("Could not load dtb file '%s'", name);
|
|
}
|
|
return fdt;
|
|
}
|
|
|
|
static void *pegasos1_build_fdt(PegasosMachineState *pm, int *fdt_size)
|
|
{
|
|
FDTInfo fi;
|
|
PCIBus *pci_bus;
|
|
void *fdt = load_dtb("pegasos1.dtb", fdt_size);
|
|
|
|
if (!fdt) {
|
|
return NULL;
|
|
}
|
|
qemu_fdt_setprop_string(fdt, "/", "name", "bplan,Pegasos");
|
|
|
|
add_cpu_info(fdt, pm->cpu, pm->bus_freq_hz);
|
|
|
|
fi.fdt = fdt;
|
|
fi.path = "/pci@80000000";
|
|
pci_bus = PCI_BUS(qdev_get_child_bus(pm->nb, "pci.0"));
|
|
pci_for_each_device_reverse(pci_bus, 0, add_pci_device, &fi);
|
|
|
|
return fdt;
|
|
}
|
|
|
|
static void *pegasos2_build_fdt(PegasosMachineState *pm, int *fdt_size)
|
|
{
|
|
FDTInfo fi;
|
|
PCIBus *pci_bus;
|
|
void *fdt = load_dtb("pegasos2.dtb", fdt_size);
|
|
|
|
if (!fdt) {
|
|
return NULL;
|
|
}
|
|
qemu_fdt_setprop_string(fdt, "/", "name", "bplan,Pegasos2");
|
|
|
|
add_cpu_info(fdt, pm->cpu, pm->bus_freq_hz);
|
|
|
|
fi.fdt = fdt;
|
|
fi.path = "/pci@c0000000";
|
|
pci_bus = mv64361_get_pci_bus(pm->nb, 0);
|
|
pci_for_each_device_reverse(pci_bus, 0, add_pci_device, &fi);
|
|
fi.path = "/pci@80000000";
|
|
pci_bus = mv64361_get_pci_bus(pm->nb, 1);
|
|
pci_for_each_device_reverse(pci_bus, 0, add_pci_device, &fi);
|
|
|
|
return fdt;
|
|
}
|