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99 lines
2.6 KiB
C
99 lines
2.6 KiB
C
/*
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* i.MX8 PCIe PHY emulation
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*
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* Copyright (c) 2025 Bernhard Beschow <shentey@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include "qemu/osdep.h"
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#include "hw/pci-host/fsl_imx8m_phy.h"
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#include "hw/resettable.h"
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#include "migration/vmstate.h"
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#define CMN_REG075 0x1d4
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#define ANA_PLL_LOCK_DONE BIT(1)
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#define ANA_PLL_AFC_DONE BIT(0)
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static uint64_t fsl_imx8m_pcie_phy_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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FslImx8mPciePhyState *s = opaque;
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if (offset == CMN_REG075) {
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return s->data[offset] | ANA_PLL_LOCK_DONE | ANA_PLL_AFC_DONE;
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}
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return s->data[offset];
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}
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static void fsl_imx8m_pcie_phy_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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{
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FslImx8mPciePhyState *s = opaque;
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s->data[offset] = value;
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}
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static const MemoryRegionOps fsl_imx8m_pcie_phy_ops = {
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.read = fsl_imx8m_pcie_phy_read,
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.write = fsl_imx8m_pcie_phy_write,
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.impl = {
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.min_access_size = 1,
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.max_access_size = 1,
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},
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.valid = {
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.min_access_size = 1,
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.max_access_size = 8,
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},
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static void fsl_imx8m_pcie_phy_realize(DeviceState *dev, Error **errp)
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{
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FslImx8mPciePhyState *s = FSL_IMX8M_PCIE_PHY(dev);
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memory_region_init_io(&s->iomem, OBJECT(s), &fsl_imx8m_pcie_phy_ops, s,
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TYPE_FSL_IMX8M_PCIE_PHY, ARRAY_SIZE(s->data));
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sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
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}
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static void fsl_imx8m_pcie_phy_reset_hold(Object *obj, ResetType type)
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{
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FslImx8mPciePhyState *s = FSL_IMX8M_PCIE_PHY(obj);
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memset(s->data, 0, sizeof(s->data));
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}
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static const VMStateDescription fsl_imx8m_pcie_phy_vmstate = {
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.name = "fsl-imx8m-pcie-phy",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (const VMStateField[]) {
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VMSTATE_UINT8_ARRAY(data, FslImx8mPciePhyState,
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FSL_IMX8M_PCIE_PHY_DATA_SIZE),
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VMSTATE_END_OF_LIST()
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}
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};
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static void fsl_imx8m_pcie_phy_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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ResettableClass *rc = RESETTABLE_CLASS(klass);
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dc->realize = fsl_imx8m_pcie_phy_realize;
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dc->vmsd = &fsl_imx8m_pcie_phy_vmstate;
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rc->phases.hold = fsl_imx8m_pcie_phy_reset_hold;
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}
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static const TypeInfo fsl_imx8m_pcie_phy_types[] = {
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{
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.name = TYPE_FSL_IMX8M_PCIE_PHY,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(FslImx8mPciePhyState),
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.class_init = fsl_imx8m_pcie_phy_class_init,
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}
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};
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DEFINE_TYPES(fsl_imx8m_pcie_phy_types)
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