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d9e6b8424f
We only allow default PCIe Root Complex(pcie.0) or pxb-pcie based extra root complexes to be associated with SMMU. Although this change does not affect functionality at present, it is required when we add support for user-creatable SMMUv3 devices in future patches. Note: Added a specific check to identify pxb-pcie to avoid matching pxb-cxl host bridges, which are also of type PCI_HOST_BRIDGE. This restriction can be relaxed once support for CXL devices on arm/virt is added and validated with SMMUv3. Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Tested-by: Nathan Chen <nathanc@nvidia.com> Tested-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Nicolin Chen <nicolinc@nvidia.com> Tested-by: Nicolin Chen <nicolinc@nvidia.com> Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com> Signed-off-by: Shameer Kolothum <skolothumtho@nvidia.com> Reviewed-by: Donald Dutile <ddutile@redhat.com> Message-id: 20250829082543.7680-2-skolothumtho@nvidia.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
1 month ago | |
|---|---|---|
| .. | ||
| Kconfig | 1 year ago | |
| cxl_downstream.c | 6 months ago | |
| cxl_root_port.c | 6 months ago | |
| cxl_upstream.c | 6 months ago | |
| gen_pcie_root_port.c | 6 months ago | |
| i82801b11.c | 6 months ago | |
| ioh3420.c | 6 months ago | |
| meson.build | 1 year ago | |
| pci_bridge_dev.c | 6 months ago | |
| pci_expander_bridge.c | 1 month ago | |
| pci_expander_bridge_stubs.c | 3 years ago | |
| pcie_pci_bridge.c | 6 months ago | |
| pcie_root_port.c | 6 months ago | |
| simba.c | 6 months ago | |
| xio3130_downstream.c | 6 months ago | |
| xio3130_upstream.c | 6 months ago | |