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255 lines
6.6 KiB
C
255 lines
6.6 KiB
C
/*
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* QEMU NVM Express Subsystem: nvme-subsys
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*
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* Copyright (c) 2021 Minwoo Im <minwoo.im.dev@gmail.com>
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*
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* This code is licensed under the GNU GPL v2. Refer COPYING.
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*/
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#include "qemu/osdep.h"
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#include "qemu/units.h"
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#include "qapi/error.h"
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#include "nvme.h"
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#define NVME_DEFAULT_RU_SIZE (96 * MiB)
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static int nvme_subsys_reserve_cntlids(NvmeCtrl *n, int start, int num)
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{
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NvmeSubsystem *subsys = n->subsys;
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NvmeSecCtrlEntry *list = n->sec_ctrl_list;
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NvmeSecCtrlEntry *sctrl;
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int i, cnt = 0;
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for (i = start; i < ARRAY_SIZE(subsys->ctrls) && cnt < num; i++) {
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if (!subsys->ctrls[i]) {
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sctrl = &list[cnt];
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sctrl->scid = cpu_to_le16(i);
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subsys->ctrls[i] = SUBSYS_SLOT_RSVD;
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cnt++;
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}
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}
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return cnt;
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}
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static void nvme_subsys_unreserve_cntlids(NvmeCtrl *n)
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{
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NvmeSubsystem *subsys = n->subsys;
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NvmeSecCtrlEntry *list = n->sec_ctrl_list;
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NvmeSecCtrlEntry *sctrl;
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int i, cntlid;
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for (i = 0; i < n->params.sriov_max_vfs; i++) {
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sctrl = &list[i];
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cntlid = le16_to_cpu(sctrl->scid);
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if (cntlid) {
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assert(subsys->ctrls[cntlid] == SUBSYS_SLOT_RSVD);
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subsys->ctrls[cntlid] = NULL;
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sctrl->scid = 0;
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}
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}
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}
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int nvme_subsys_register_ctrl(NvmeCtrl *n, Error **errp)
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{
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NvmeSubsystem *subsys = n->subsys;
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NvmeSecCtrlEntry *sctrl = nvme_sctrl(n);
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int cntlid, nsid, num_rsvd, num_vfs = n->params.sriov_max_vfs;
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if (pci_is_vf(&n->parent_obj)) {
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cntlid = le16_to_cpu(sctrl->scid);
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} else {
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n->sec_ctrl_list = g_new0(NvmeSecCtrlEntry, num_vfs);
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for (cntlid = 0; cntlid < ARRAY_SIZE(subsys->ctrls); cntlid++) {
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if (!subsys->ctrls[cntlid]) {
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break;
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}
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}
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if (cntlid == ARRAY_SIZE(subsys->ctrls)) {
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error_setg(errp, "no more free controller id");
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return -1;
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}
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num_rsvd = nvme_subsys_reserve_cntlids(n, cntlid + 1, num_vfs);
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if (num_rsvd != num_vfs) {
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nvme_subsys_unreserve_cntlids(n);
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error_setg(errp,
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"no more free controller ids for secondary controllers");
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return -1;
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}
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}
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if (!subsys->serial) {
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subsys->serial = g_strdup(n->params.serial);
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} else if (strcmp(subsys->serial, n->params.serial)) {
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error_setg(errp, "invalid controller serial");
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return -1;
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}
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subsys->ctrls[cntlid] = n;
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for (nsid = 1; nsid < ARRAY_SIZE(subsys->namespaces); nsid++) {
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NvmeNamespace *ns = subsys->namespaces[nsid];
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if (ns && ns->params.shared && !ns->params.detached) {
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nvme_attach_ns(n, ns);
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}
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}
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return cntlid;
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}
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void nvme_subsys_unregister_ctrl(NvmeSubsystem *subsys, NvmeCtrl *n)
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{
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if (pci_is_vf(&n->parent_obj)) {
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subsys->ctrls[n->cntlid] = SUBSYS_SLOT_RSVD;
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} else {
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subsys->ctrls[n->cntlid] = NULL;
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nvme_subsys_unreserve_cntlids(n);
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}
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n->cntlid = -1;
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}
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static bool nvme_calc_rgif(uint16_t nruh, uint16_t nrg, uint8_t *rgif)
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{
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uint16_t val;
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unsigned int i;
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if (unlikely(nrg == 1)) {
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/* PIDRG_NORGI scenario, all of pid is used for PHID */
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*rgif = 0;
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return true;
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}
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val = nrg;
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i = 0;
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while (val) {
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val >>= 1;
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i++;
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}
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*rgif = i;
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/* ensure remaining bits suffice to represent number of phids in a RG */
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if (unlikely((UINT16_MAX >> i) < nruh)) {
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*rgif = 0;
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return false;
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}
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return true;
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}
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static bool nvme_subsys_setup_fdp(NvmeSubsystem *subsys, Error **errp)
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{
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NvmeEnduranceGroup *endgrp = &subsys->endgrp;
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if (!subsys->params.fdp.runs) {
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error_setg(errp, "fdp.runs must be non-zero");
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return false;
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}
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endgrp->fdp.runs = subsys->params.fdp.runs;
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if (!subsys->params.fdp.nrg) {
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error_setg(errp, "fdp.nrg must be non-zero");
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return false;
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}
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endgrp->fdp.nrg = subsys->params.fdp.nrg;
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if (!subsys->params.fdp.nruh ||
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subsys->params.fdp.nruh > NVME_FDP_MAXPIDS) {
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error_setg(errp, "fdp.nruh must be non-zero and less than %u",
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NVME_FDP_MAXPIDS);
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return false;
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}
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endgrp->fdp.nruh = subsys->params.fdp.nruh;
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if (!nvme_calc_rgif(endgrp->fdp.nruh, endgrp->fdp.nrg, &endgrp->fdp.rgif)) {
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error_setg(errp,
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"cannot derive a valid rgif (nruh %"PRIu16" nrg %"PRIu32")",
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endgrp->fdp.nruh, endgrp->fdp.nrg);
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return false;
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}
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endgrp->fdp.ruhs = g_new(NvmeRuHandle, endgrp->fdp.nruh);
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for (uint16_t ruhid = 0; ruhid < endgrp->fdp.nruh; ruhid++) {
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endgrp->fdp.ruhs[ruhid] = (NvmeRuHandle) {
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.ruht = NVME_RUHT_INITIALLY_ISOLATED,
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.ruha = NVME_RUHA_UNUSED,
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};
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endgrp->fdp.ruhs[ruhid].rus = g_new(NvmeReclaimUnit, endgrp->fdp.nrg);
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}
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endgrp->fdp.enabled = true;
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return true;
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}
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static bool nvme_subsys_setup(NvmeSubsystem *subsys, Error **errp)
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{
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const char *nqn = subsys->params.nqn ?
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subsys->params.nqn : subsys->parent_obj.id;
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snprintf((char *)subsys->subnqn, sizeof(subsys->subnqn),
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"nqn.2019-08.org.qemu:%s", nqn);
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if (subsys->params.fdp.enabled && !nvme_subsys_setup_fdp(subsys, errp)) {
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return false;
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}
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return true;
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}
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static void nvme_subsys_realize(DeviceState *dev, Error **errp)
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{
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NvmeSubsystem *subsys = NVME_SUBSYS(dev);
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qbus_init(&subsys->bus, sizeof(NvmeBus), TYPE_NVME_BUS, dev, dev->id);
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nvme_subsys_setup(subsys, errp);
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}
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static Property nvme_subsystem_props[] = {
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DEFINE_PROP_STRING("nqn", NvmeSubsystem, params.nqn),
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DEFINE_PROP_BOOL("fdp", NvmeSubsystem, params.fdp.enabled, false),
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DEFINE_PROP_SIZE("fdp.runs", NvmeSubsystem, params.fdp.runs,
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NVME_DEFAULT_RU_SIZE),
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DEFINE_PROP_UINT32("fdp.nrg", NvmeSubsystem, params.fdp.nrg, 1),
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DEFINE_PROP_UINT16("fdp.nruh", NvmeSubsystem, params.fdp.nruh, 0),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void nvme_subsys_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
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dc->realize = nvme_subsys_realize;
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dc->desc = "Virtual NVMe subsystem";
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dc->hotpluggable = false;
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device_class_set_props(dc, nvme_subsystem_props);
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}
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static const TypeInfo nvme_subsys_info = {
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.name = TYPE_NVME_SUBSYS,
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.parent = TYPE_DEVICE,
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.class_init = nvme_subsys_class_init,
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.instance_size = sizeof(NvmeSubsystem),
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};
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static void nvme_subsys_register_types(void)
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{
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type_register_static(&nvme_subsys_info);
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}
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type_init(nvme_subsys_register_types)
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