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56 lines
1.8 KiB
C
56 lines
1.8 KiB
C
#ifndef HW_I82596_H
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#define HW_I82596_H
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#define I82596_IOPORT_SIZE 0x20
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#include "exec/memory.h"
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#include "exec/address-spaces.h"
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#define PORT_RESET 0x00 /* reset 82596 */
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#define PORT_SELFTEST 0x01 /* selftest */
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#define PORT_ALTSCP 0x02 /* alternate SCB address */
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#define PORT_ALTDUMP 0x03 /* Alternate DUMP address */
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#define PORT_CA 0x10 /* QEMU-internal CA signal */
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typedef struct I82596State_st I82596State;
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struct I82596State_st {
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MemoryRegion mmio;
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MemoryRegion *as;
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qemu_irq irq;
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NICState *nic;
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NICConf conf;
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QEMUTimer *flush_queue_timer;
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hwaddr scp; /* pointer to SCP */
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uint8_t sysbus;
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uint32_t scb; /* SCB */
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uint16_t scb_status;
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uint8_t cu_status, rx_status;
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uint16_t lnkst;
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uint32_t cmd_p; /* addr of current command */
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int ca;
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int ca_active;
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int send_irq;
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/* Hash register (multicast mask array, multiple individual addresses). */
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uint8_t mult[8];
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uint8_t config[14]; /* config bytes from CONFIGURE command */
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uint8_t tx_buffer[0x4000];
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};
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void i82596_h_reset(void *opaque);
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void i82596_ioport_writew(void *opaque, uint32_t addr, uint32_t val);
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uint32_t i82596_ioport_readw(void *opaque, uint32_t addr);
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void i82596_ioport_writel(void *opaque, uint32_t addr, uint32_t val);
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uint32_t i82596_ioport_readl(void *opaque, uint32_t addr);
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uint32_t i82596_bcr_readw(I82596State *s, uint32_t rap);
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ssize_t i82596_receive(NetClientState *nc, const uint8_t *buf, size_t size_);
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bool i82596_can_receive(NetClientState *nc);
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void i82596_set_link_status(NetClientState *nc);
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void i82596_common_init(DeviceState *dev, I82596State *s, NetClientInfo *info);
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extern const VMStateDescription vmstate_i82596;
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#endif
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