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687 lines
25 KiB
C
687 lines
25 KiB
C
/*
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* Generic Loongson-3 Platform support
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*
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* Copyright (c) 2018-2020 Huacai Chen (chenhc@lemote.com)
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* Copyright (c) 2018-2020 Jiaxun Yang <jiaxun.yang@flygoat.com>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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/*
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* Generic virtualized PC Platform based on Loongson-3 CPU (MIPS64R2 with
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* extensions, 800~2000MHz)
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*/
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#include "qemu/osdep.h"
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#include "qemu/units.h"
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#include "qemu/cutils.h"
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#include "qemu/datadir.h"
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#include "qapi/error.h"
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#include "elf.h"
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#include "hw/char/serial-mm.h"
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#include "hw/intc/loongson_liointc.h"
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#include "hw/mips/mips.h"
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#include "hw/mips/fw_cfg.h"
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#include "hw/mips/loongson3_bootp.h"
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#include "hw/misc/unimp.h"
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#include "hw/intc/i8259.h"
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#include "hw/intc/loongson_ipi.h"
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#include "hw/loader.h"
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#include "hw/isa/superio.h"
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#include "hw/pci/msi.h"
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#include "hw/pci/pci.h"
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#include "hw/pci/pci_host.h"
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#include "hw/pci-host/gpex.h"
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#include "hw/usb.h"
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#include "net/net.h"
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#include "sysemu/kvm.h"
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#include "sysemu/qtest.h"
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#include "sysemu/reset.h"
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#include "sysemu/runstate.h"
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#include "qemu/error-report.h"
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#define PM_CNTL_MODE 0x10
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#define LOONGSON_MAX_VCPUS 16
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/*
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* Loongson-3's virtual machine BIOS can be obtained here:
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* 1, https://github.com/loongson-community/firmware-nonfree
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* 2, http://dev.lemote.com:8000/files/firmware/UEFI/KVM/bios_loongson3.bin
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*/
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#define LOONGSON3_BIOSNAME "bios_loongson3.bin"
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#define UART_IRQ 0
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#define RTC_IRQ 1
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#define PCIE_IRQ_BASE 2
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const MemMapEntry virt_memmap[] = {
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[VIRT_LOWMEM] = { 0x00000000, 0x10000000 },
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[VIRT_PM] = { 0x10080000, 0x100 },
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[VIRT_FW_CFG] = { 0x10080100, 0x100 },
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[VIRT_RTC] = { 0x10081000, 0x1000 },
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[VIRT_PCIE_PIO] = { 0x18000000, 0x80000 },
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[VIRT_PCIE_ECAM] = { 0x1a000000, 0x2000000 },
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[VIRT_BIOS_ROM] = { 0x1fc00000, 0x200000 },
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[VIRT_UART] = { 0x1fe001e0, 0x8 },
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[VIRT_IPI] = { 0x3ff01000, 0x400 },
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[VIRT_LIOINTC] = { 0x3ff01400, 0x64 },
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[VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 },
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[VIRT_HIGHMEM] = { 0x80000000, 0x0 }, /* Variable */
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};
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static const MemMapEntry loader_memmap[] = {
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[LOADER_KERNEL] = { 0x00000000, 0x4000000 },
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[LOADER_INITRD] = { 0x04000000, 0x0 }, /* Variable */
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[LOADER_CMDLINE] = { 0x0ff00000, 0x100000 },
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};
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static const MemMapEntry loader_rommap[] = {
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[LOADER_BOOTROM] = { 0x1fc00000, 0x1000 },
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[LOADER_PARAM] = { 0x1fc01000, 0x10000 },
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};
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struct LoongsonMachineState {
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MachineState parent_obj;
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MemoryRegion *pio_alias;
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MemoryRegion *mmio_alias;
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MemoryRegion *ecam_alias;
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MemoryRegion *core_iocsr[LOONGSON_MAX_VCPUS];
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};
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typedef struct LoongsonMachineState LoongsonMachineState;
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#define TYPE_LOONGSON_MACHINE MACHINE_TYPE_NAME("loongson3-virt")
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DECLARE_INSTANCE_CHECKER(LoongsonMachineState, LOONGSON_MACHINE, TYPE_LOONGSON_MACHINE)
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static struct _loaderparams {
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uint64_t cpu_freq;
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uint64_t ram_size;
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const char *kernel_cmdline;
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const char *kernel_filename;
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const char *initrd_filename;
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uint64_t kernel_entry;
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uint64_t a0, a1, a2;
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} loaderparams;
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static uint64_t loongson3_pm_read(void *opaque, hwaddr addr, unsigned size)
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{
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return 0;
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}
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static void loongson3_pm_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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if (addr != PM_CNTL_MODE) {
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return;
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}
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switch (val) {
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case 0x00:
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qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
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return;
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case 0x01:
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qemu_system_suspend_request();
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return;
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case 0xff:
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qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
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return;
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default:
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return;
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}
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}
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static const MemoryRegionOps loongson3_pm_ops = {
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.read = loongson3_pm_read,
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.write = loongson3_pm_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid = {
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.min_access_size = 1,
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.max_access_size = 1
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}
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};
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#define DEF_LOONGSON3_FREQ (800 * 1000 * 1000)
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static uint64_t get_cpu_freq_hz(void)
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{
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#ifdef CONFIG_KVM
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int ret;
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uint64_t freq;
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struct kvm_one_reg freq_reg = {
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.id = KVM_REG_MIPS_COUNT_HZ,
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.addr = (uintptr_t)(&freq)
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};
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if (kvm_enabled()) {
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ret = kvm_vcpu_ioctl(first_cpu, KVM_GET_ONE_REG, &freq_reg);
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if (ret >= 0) {
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return freq * 2;
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}
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}
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#endif
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return DEF_LOONGSON3_FREQ;
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}
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static void init_boot_param(void)
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{
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static void *p;
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struct boot_params *bp;
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p = g_malloc0(loader_rommap[LOADER_PARAM].size);
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bp = p;
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bp->efi.smbios.vers = cpu_to_le16(1);
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init_reset_system(&(bp->reset_system));
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p += ROUND_UP(sizeof(struct boot_params), 64);
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init_loongson_params(&(bp->efi.smbios.lp), p,
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loaderparams.cpu_freq, loaderparams.ram_size);
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rom_add_blob_fixed("params_rom", bp,
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loader_rommap[LOADER_PARAM].size,
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loader_rommap[LOADER_PARAM].base);
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g_free(bp);
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loaderparams.a2 = cpu_mips_phys_to_kseg0(NULL,
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loader_rommap[LOADER_PARAM].base);
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}
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static void init_boot_rom(void)
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{
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const unsigned int boot_code[] = {
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0x40086000, /* mfc0 t0, CP0_STATUS */
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0x240900E4, /* li t1, 0xe4 #set kx, sx, ux, erl */
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0x01094025, /* or t0, t0, t1 */
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0x3C090040, /* lui t1, 0x40 #set bev */
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0x01094025, /* or t0, t0, t1 */
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0x40886000, /* mtc0 t0, CP0_STATUS */
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0x00000000,
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0x40806800, /* mtc0 zero, CP0_CAUSE */
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0x00000000,
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0x400A7801, /* mfc0 t2, $15, 1 */
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0x314A00FF, /* andi t2, 0x0ff */
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0x3C089000, /* dli t0, 0x900000003ff01000 */
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0x00084438,
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0x35083FF0,
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0x00084438,
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0x35081000,
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0x314B0003, /* andi t3, t2, 0x3 #local cpuid */
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0x000B5A00, /* sll t3, 8 */
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0x010B4025, /* or t0, t0, t3 */
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0x314C000C, /* andi t4, t2, 0xc #node id */
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0x000C62BC, /* dsll t4, 42 */
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0x010C4025, /* or t0, t0, t4 */
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/* WaitForInit: */
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0xDD020020, /* ld v0, FN_OFF(t0) #FN_OFF 0x020 */
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0x1040FFFE, /* beqz v0, WaitForInit */
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0x00000000, /* nop */
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0xDD1D0028, /* ld sp, SP_OFF(t0) #FN_OFF 0x028 */
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0xDD1C0030, /* ld gp, GP_OFF(t0) #FN_OFF 0x030 */
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0xDD050038, /* ld a1, A1_OFF(t0) #FN_OFF 0x038 */
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0x00400008, /* jr v0 #byebye */
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0x00000000, /* nop */
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0x1000FFFF, /* 1: b 1b */
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0x00000000, /* nop */
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/* Reset */
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0x3C0C9000, /* dli t0, 0x9000000010080010 */
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0x358C0000,
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0x000C6438,
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0x358C1008,
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0x000C6438,
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0x358C0010,
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0x240D0000, /* li t1, 0x00 */
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0xA18D0000, /* sb t1, (t0) */
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0x1000FFFF, /* 1: b 1b */
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0x00000000, /* nop */
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/* Shutdown */
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0x3C0C9000, /* dli t0, 0x9000000010080010 */
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0x358C0000,
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0x000C6438,
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0x358C1008,
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0x000C6438,
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0x358C0010,
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0x240D00FF, /* li t1, 0xff */
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0xA18D0000, /* sb t1, (t0) */
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0x1000FFFF, /* 1: b 1b */
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0x00000000, /* nop */
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/* Suspend */
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0x3C0C9000, /* dli t0, 0x9000000010080010 */
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0x358C0000,
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0x000C6438,
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0x358C1008,
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0x000C6438,
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0x358C0010,
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0x240D0001, /* li t1, 0x01 */
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0xA18D0000, /* sb t1, (t0) */
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0x03e00008, /* jr ra */
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0x00000000 /* nop */
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};
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rom_add_blob_fixed("boot_rom", boot_code, sizeof(boot_code),
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loader_rommap[LOADER_BOOTROM].base);
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}
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static void fw_cfg_boot_set(void *opaque, const char *boot_device,
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Error **errp)
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{
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fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
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}
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static void fw_conf_init(unsigned long ram_size)
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{
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static const uint8_t suspend[6] = {128, 0, 0, 129, 128, 128};
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FWCfgState *fw_cfg;
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hwaddr cfg_addr = virt_memmap[VIRT_FW_CFG].base;
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fw_cfg = fw_cfg_init_mem_wide(cfg_addr, cfg_addr + 8, 8, 0, NULL);
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fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)current_machine->smp.cpus);
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fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)current_machine->smp.max_cpus);
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fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
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fw_cfg_add_i32(fw_cfg, FW_CFG_MACHINE_VERSION, 1);
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fw_cfg_add_i64(fw_cfg, FW_CFG_CPU_FREQ, get_cpu_freq_hz());
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fw_cfg_add_file(fw_cfg, "etc/system-states",
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g_memdup2(suspend, sizeof(suspend)), sizeof(suspend));
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qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
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}
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static int set_prom_cmdline(ram_addr_t initrd_offset, long initrd_size)
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{
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int ret = 0;
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void *cmdline_buf;
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hwaddr cmdline_vaddr;
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unsigned int *parg_env;
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/* Allocate cmdline_buf for command line. */
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cmdline_buf = g_malloc0(loader_memmap[LOADER_CMDLINE].size);
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cmdline_vaddr = cpu_mips_phys_to_kseg0(NULL,
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loader_memmap[LOADER_CMDLINE].base);
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/*
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* Layout of cmdline_buf looks like this:
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* argv[0], argv[1], 0, env[0], env[1], ... env[i], 0,
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* argv[0]'s data, argv[1]'s data, env[0]'data, ..., env[i]'s data, 0
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*/
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parg_env = (void *)cmdline_buf;
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ret = (3 + 1) * 4;
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*parg_env++ = cmdline_vaddr + ret;
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ret += (1 + snprintf(cmdline_buf + ret, 256 - ret, "g"));
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/* argv1 */
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*parg_env++ = cmdline_vaddr + ret;
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if (initrd_size > 0)
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ret += (1 + snprintf(cmdline_buf + ret, 256 - ret,
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"rd_start=0x" TARGET_FMT_lx " rd_size=%li %s",
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cpu_mips_phys_to_kseg0(NULL, initrd_offset),
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initrd_size, loaderparams.kernel_cmdline));
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else
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ret += (1 + snprintf(cmdline_buf + ret, 256 - ret, "%s",
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loaderparams.kernel_cmdline));
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/* argv2 */
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*parg_env++ = cmdline_vaddr + 4 * ret;
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rom_add_blob_fixed("cmdline", cmdline_buf,
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loader_memmap[LOADER_CMDLINE].size,
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loader_memmap[LOADER_CMDLINE].base);
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g_free(cmdline_buf);
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loaderparams.a0 = 2;
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loaderparams.a1 = cmdline_vaddr;
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return 0;
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}
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static uint64_t load_kernel(CPUMIPSState *env)
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{
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long kernel_size;
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ram_addr_t initrd_offset;
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uint64_t kernel_entry, kernel_low, kernel_high, initrd_size;
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kernel_size = load_elf(loaderparams.kernel_filename, NULL,
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cpu_mips_kseg0_to_phys, NULL,
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&kernel_entry,
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&kernel_low, &kernel_high,
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NULL, 0, EM_MIPS, 1, 0);
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if (kernel_size < 0) {
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error_report("could not load kernel '%s': %s",
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loaderparams.kernel_filename,
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load_elf_strerror(kernel_size));
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exit(1);
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}
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/* load initrd */
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initrd_size = 0;
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initrd_offset = 0;
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if (loaderparams.initrd_filename) {
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initrd_size = get_image_size(loaderparams.initrd_filename);
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if (initrd_size > 0) {
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initrd_offset = MAX(loader_memmap[LOADER_INITRD].base,
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ROUND_UP(kernel_high, INITRD_PAGE_SIZE));
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if (initrd_offset + initrd_size > loaderparams.ram_size) {
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error_report("memory too small for initial ram disk '%s'",
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loaderparams.initrd_filename);
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exit(1);
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}
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initrd_size = load_image_targphys(loaderparams.initrd_filename,
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initrd_offset,
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loaderparams.ram_size - initrd_offset);
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}
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if (initrd_size == (target_ulong) -1) {
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error_report("could not load initial ram disk '%s'",
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loaderparams.initrd_filename);
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exit(1);
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}
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}
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/* Setup prom cmdline. */
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set_prom_cmdline(initrd_offset, initrd_size);
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return kernel_entry;
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}
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static void main_cpu_reset(void *opaque)
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{
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MIPSCPU *cpu = opaque;
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CPUMIPSState *env = &cpu->env;
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cpu_reset(CPU(cpu));
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/* Loongson-3 reset stuff */
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if (loaderparams.kernel_filename) {
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if (cpu == MIPS_CPU(first_cpu)) {
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env->active_tc.gpr[4] = loaderparams.a0;
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env->active_tc.gpr[5] = loaderparams.a1;
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env->active_tc.gpr[6] = loaderparams.a2;
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env->active_tc.PC = loaderparams.kernel_entry;
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}
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env->CP0_Status &= ~((1 << CP0St_BEV) | (1 << CP0St_ERL));
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}
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}
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static inline void loongson3_virt_devices_init(MachineState *machine,
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DeviceState *pic)
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{
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int i;
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qemu_irq irq;
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PCIBus *pci_bus;
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DeviceState *dev;
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MemoryRegion *mmio_reg, *ecam_reg;
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MachineClass *mc = MACHINE_GET_CLASS(machine);
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LoongsonMachineState *s = LOONGSON_MACHINE(machine);
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dev = qdev_new(TYPE_GPEX_HOST);
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sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
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pci_bus = PCI_HOST_BRIDGE(dev)->bus;
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s->ecam_alias = g_new0(MemoryRegion, 1);
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ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
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memory_region_init_alias(s->ecam_alias, OBJECT(dev), "pcie-ecam",
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ecam_reg, 0, virt_memmap[VIRT_PCIE_ECAM].size);
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memory_region_add_subregion(get_system_memory(),
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virt_memmap[VIRT_PCIE_ECAM].base,
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s->ecam_alias);
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s->mmio_alias = g_new0(MemoryRegion, 1);
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mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
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memory_region_init_alias(s->mmio_alias, OBJECT(dev), "pcie-mmio",
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mmio_reg, virt_memmap[VIRT_PCIE_MMIO].base,
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virt_memmap[VIRT_PCIE_MMIO].size);
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memory_region_add_subregion(get_system_memory(),
|
|
virt_memmap[VIRT_PCIE_MMIO].base,
|
|
s->mmio_alias);
|
|
|
|
s->pio_alias = g_new0(MemoryRegion, 1);
|
|
memory_region_init_alias(s->pio_alias, OBJECT(dev), "pcie-pio",
|
|
get_system_io(), 0,
|
|
virt_memmap[VIRT_PCIE_PIO].size);
|
|
memory_region_add_subregion(get_system_memory(),
|
|
virt_memmap[VIRT_PCIE_PIO].base, s->pio_alias);
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, virt_memmap[VIRT_PCIE_PIO].base);
|
|
|
|
for (i = 0; i < GPEX_NUM_IRQS; i++) {
|
|
irq = qdev_get_gpio_in(pic, PCIE_IRQ_BASE + i);
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq);
|
|
gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ_BASE + i);
|
|
}
|
|
msi_nonbroken = true;
|
|
|
|
pci_vga_init(pci_bus);
|
|
|
|
if (defaults_enabled() && object_class_by_name("pci-ohci")) {
|
|
USBBus *usb_bus;
|
|
|
|
pci_create_simple(pci_bus, -1, "pci-ohci");
|
|
usb_bus = USB_BUS(object_resolve_type_unambiguous(TYPE_USB_BUS,
|
|
&error_abort));
|
|
usb_create_simple(usb_bus, "usb-kbd");
|
|
usb_create_simple(usb_bus, "usb-tablet");
|
|
}
|
|
|
|
pci_init_nic_devices(pci_bus, mc->default_nic);
|
|
}
|
|
|
|
static void mips_loongson3_virt_init(MachineState *machine)
|
|
{
|
|
int i;
|
|
long bios_size;
|
|
MIPSCPU *cpu;
|
|
Clock *cpuclk;
|
|
CPUMIPSState *env;
|
|
DeviceState *liointc;
|
|
DeviceState *ipi = NULL;
|
|
char *filename;
|
|
const char *kernel_cmdline = machine->kernel_cmdline;
|
|
const char *kernel_filename = machine->kernel_filename;
|
|
const char *initrd_filename = machine->initrd_filename;
|
|
ram_addr_t ram_size = machine->ram_size;
|
|
LoongsonMachineState *s = LOONGSON_MACHINE(machine);
|
|
MemoryRegion *address_space_mem = get_system_memory();
|
|
MemoryRegion *ram = g_new(MemoryRegion, 1);
|
|
MemoryRegion *bios = g_new(MemoryRegion, 1);
|
|
MemoryRegion *iomem = g_new(MemoryRegion, 1);
|
|
MemoryRegion *iocsr = g_new(MemoryRegion, 1);
|
|
|
|
/* TODO: TCG will support all CPU types */
|
|
if (!kvm_enabled()) {
|
|
if (!machine->cpu_type) {
|
|
machine->cpu_type = MIPS_CPU_TYPE_NAME("Loongson-3A1000");
|
|
}
|
|
if (!cpu_type_supports_isa(machine->cpu_type, INSN_LOONGSON3A)) {
|
|
error_report("Loongson-3/TCG needs a Loongson-3 series cpu");
|
|
exit(1);
|
|
}
|
|
} else {
|
|
if (!machine->cpu_type) {
|
|
machine->cpu_type = MIPS_CPU_TYPE_NAME("Loongson-3A4000");
|
|
}
|
|
if (!strstr(machine->cpu_type, "Loongson-3A4000")) {
|
|
error_report("Loongson-3/KVM needs cpu type Loongson-3A4000");
|
|
exit(1);
|
|
}
|
|
}
|
|
|
|
if (ram_size < 512 * MiB) {
|
|
error_report("Loongson-3 machine needs at least 512MB memory");
|
|
exit(1);
|
|
}
|
|
|
|
/*
|
|
* The whole MMIO range among configure registers doesn't generate
|
|
* exception when accessing invalid memory. Create some unimplememted
|
|
* devices to emulate this feature.
|
|
*/
|
|
create_unimplemented_device("mmio fallback 0", 0x10000000, 256 * MiB);
|
|
create_unimplemented_device("mmio fallback 1", 0x30000000, 256 * MiB);
|
|
|
|
memory_region_init(iocsr, OBJECT(machine), "loongson3.iocsr", UINT32_MAX);
|
|
|
|
/* IPI controller is in kernel for KVM */
|
|
if (!kvm_enabled()) {
|
|
ipi = qdev_new(TYPE_LOONGSON_IPI);
|
|
qdev_prop_set_uint32(ipi, "num-cpu", machine->smp.cpus);
|
|
sysbus_realize_and_unref(SYS_BUS_DEVICE(ipi), &error_fatal);
|
|
memory_region_add_subregion(iocsr, SMP_IPI_MAILBOX,
|
|
sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 0));
|
|
memory_region_add_subregion(iocsr, MAIL_SEND_ADDR,
|
|
sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 1));
|
|
}
|
|
|
|
liointc = qdev_new("loongson.liointc");
|
|
sysbus_realize_and_unref(SYS_BUS_DEVICE(liointc), &error_fatal);
|
|
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(liointc), 0, virt_memmap[VIRT_LIOINTC].base);
|
|
|
|
serial_mm_init(address_space_mem, virt_memmap[VIRT_UART].base, 0,
|
|
qdev_get_gpio_in(liointc, UART_IRQ), 115200, serial_hd(0),
|
|
DEVICE_NATIVE_ENDIAN);
|
|
|
|
sysbus_create_simple("goldfish_rtc", virt_memmap[VIRT_RTC].base,
|
|
qdev_get_gpio_in(liointc, RTC_IRQ));
|
|
|
|
cpuclk = clock_new(OBJECT(machine), "cpu-refclk");
|
|
clock_set_hz(cpuclk, DEF_LOONGSON3_FREQ);
|
|
|
|
for (i = 0; i < machine->smp.cpus; i++) {
|
|
int node = i / LOONGSON3_CORE_PER_NODE;
|
|
int core = i % LOONGSON3_CORE_PER_NODE;
|
|
int ip;
|
|
|
|
/* init CPUs */
|
|
cpu = mips_cpu_create_with_clock(machine->cpu_type, cpuclk, false);
|
|
|
|
/* Init internal devices */
|
|
cpu_mips_irq_init_cpu(cpu);
|
|
cpu_mips_clock_init(cpu);
|
|
qemu_register_reset(main_cpu_reset, cpu);
|
|
|
|
if (!kvm_enabled()) {
|
|
hwaddr base = ((hwaddr)node << 44) + virt_memmap[VIRT_IPI].base;
|
|
base += core * 0x100;
|
|
qdev_connect_gpio_out(ipi, i, cpu->env.irq[6]);
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(ipi), i + 2, base);
|
|
}
|
|
|
|
if (ase_lcsr_available(&MIPS_CPU(cpu)->env)) {
|
|
MemoryRegion *core_iocsr = g_new(MemoryRegion, 1);
|
|
g_autofree char *name = g_strdup_printf("core%d_iocsr", i);
|
|
memory_region_init_alias(core_iocsr, OBJECT(cpu), name,
|
|
iocsr, 0, UINT32_MAX);
|
|
memory_region_add_subregion(&MIPS_CPU(cpu)->env.iocsr.mr,
|
|
0, core_iocsr);
|
|
s->core_iocsr[i] = core_iocsr;
|
|
}
|
|
|
|
if (node > 0) {
|
|
continue; /* Only node-0 can be connected to LIOINTC */
|
|
}
|
|
|
|
for (ip = 0; ip < 4 ; ip++) {
|
|
int pin = core * LOONGSON3_CORE_PER_NODE + ip;
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(liointc),
|
|
pin, cpu->env.irq[ip + 2]);
|
|
}
|
|
}
|
|
env = &MIPS_CPU(first_cpu)->env;
|
|
|
|
/* Allocate RAM/BIOS, 0x00000000~0x10000000 is alias of 0x80000000~0x90000000 */
|
|
memory_region_init_rom(bios, NULL, "loongson3.bios",
|
|
virt_memmap[VIRT_BIOS_ROM].size, &error_fatal);
|
|
memory_region_init_alias(ram, NULL, "loongson3.lowmem",
|
|
machine->ram, 0, virt_memmap[VIRT_LOWMEM].size);
|
|
memory_region_init_io(iomem, NULL, &loongson3_pm_ops,
|
|
NULL, "loongson3_pm", virt_memmap[VIRT_PM].size);
|
|
qemu_register_wakeup_support();
|
|
|
|
memory_region_add_subregion(address_space_mem,
|
|
virt_memmap[VIRT_LOWMEM].base, ram);
|
|
memory_region_add_subregion(address_space_mem,
|
|
virt_memmap[VIRT_BIOS_ROM].base, bios);
|
|
memory_region_add_subregion(address_space_mem,
|
|
virt_memmap[VIRT_HIGHMEM].base, machine->ram);
|
|
memory_region_add_subregion(address_space_mem,
|
|
virt_memmap[VIRT_PM].base, iomem);
|
|
|
|
/*
|
|
* We do not support flash operation, just loading bios.bin as raw BIOS.
|
|
* Please use -L to set the BIOS path and -bios to set bios name.
|
|
*/
|
|
|
|
if (kernel_filename) {
|
|
loaderparams.cpu_freq = get_cpu_freq_hz();
|
|
loaderparams.ram_size = ram_size;
|
|
loaderparams.kernel_filename = kernel_filename;
|
|
loaderparams.kernel_cmdline = kernel_cmdline;
|
|
loaderparams.initrd_filename = initrd_filename;
|
|
loaderparams.kernel_entry = load_kernel(env);
|
|
|
|
init_boot_rom();
|
|
init_boot_param();
|
|
} else {
|
|
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS,
|
|
machine->firmware ?: LOONGSON3_BIOSNAME);
|
|
if (filename) {
|
|
bios_size = load_image_targphys(filename,
|
|
virt_memmap[VIRT_BIOS_ROM].base,
|
|
virt_memmap[VIRT_BIOS_ROM].size);
|
|
g_free(filename);
|
|
} else {
|
|
bios_size = -1;
|
|
}
|
|
|
|
if ((bios_size < 0 || bios_size > virt_memmap[VIRT_BIOS_ROM].size) &&
|
|
!kernel_filename && !qtest_enabled()) {
|
|
error_report("Could not load MIPS bios '%s'", machine->firmware);
|
|
exit(1);
|
|
}
|
|
|
|
fw_conf_init(ram_size);
|
|
}
|
|
|
|
loongson3_virt_devices_init(machine, liointc);
|
|
}
|
|
|
|
static void loongson3v_machine_class_init(ObjectClass *oc, void *data)
|
|
{
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
|
|
mc->desc = "Loongson-3 Virtualization Platform";
|
|
mc->init = mips_loongson3_virt_init;
|
|
mc->block_default_type = IF_IDE;
|
|
mc->max_cpus = LOONGSON_MAX_VCPUS;
|
|
mc->default_ram_id = "loongson3.highram";
|
|
mc->default_ram_size = 1600 * MiB;
|
|
mc->minimum_page_bits = 14;
|
|
mc->default_nic = "virtio-net-pci";
|
|
}
|
|
|
|
static const TypeInfo loongson3_machine_types[] = {
|
|
{
|
|
.name = TYPE_LOONGSON_MACHINE,
|
|
.parent = TYPE_MACHINE,
|
|
.instance_size = sizeof(LoongsonMachineState),
|
|
.class_init = loongson3v_machine_class_init,
|
|
}
|
|
};
|
|
|
|
DEFINE_TYPES(loongson3_machine_types)
|