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352 lines
10 KiB
C
352 lines
10 KiB
C
/*
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* QEMU IDE Emulation: PCI cmd646 support.
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*
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* Copyright (c) 2003 Fabrice Bellard
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* Copyright (c) 2006 Openedhand Ltd.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "hw/pci/pci.h"
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#include "hw/qdev-properties.h"
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#include "migration/vmstate.h"
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#include "qemu/module.h"
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#include "hw/isa/isa.h"
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#include "sysemu/dma.h"
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#include "sysemu/reset.h"
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#include "hw/ide/pci.h"
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#include "ide-internal.h"
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#include "trace.h"
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/* CMD646 specific */
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#define CFR 0x50
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#define CFR_INTR_CH0 0x04
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#define CNTRL 0x51
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#define CNTRL_EN_CH0 0x04
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#define CNTRL_EN_CH1 0x08
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#define ARTTIM23 0x57
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#define ARTTIM23_INTR_CH1 0x10
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#define MRDMODE 0x71
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#define MRDMODE_INTR_CH0 0x04
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#define MRDMODE_INTR_CH1 0x08
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#define MRDMODE_BLK_CH0 0x10
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#define MRDMODE_BLK_CH1 0x20
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#define UDIDETCR0 0x73
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#define UDIDETCR1 0x7B
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static void cmd646_update_irq(PCIDevice *pd);
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static void cmd646_update_dma_interrupts(PCIDevice *pd)
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{
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/* Sync DMA interrupt status from UDMA interrupt status */
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if (pd->config[MRDMODE] & MRDMODE_INTR_CH0) {
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pd->config[CFR] |= CFR_INTR_CH0;
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} else {
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pd->config[CFR] &= ~CFR_INTR_CH0;
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}
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if (pd->config[MRDMODE] & MRDMODE_INTR_CH1) {
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pd->config[ARTTIM23] |= ARTTIM23_INTR_CH1;
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} else {
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pd->config[ARTTIM23] &= ~ARTTIM23_INTR_CH1;
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}
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}
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static void cmd646_update_udma_interrupts(PCIDevice *pd)
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{
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/* Sync UDMA interrupt status from DMA interrupt status */
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if (pd->config[CFR] & CFR_INTR_CH0) {
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pd->config[MRDMODE] |= MRDMODE_INTR_CH0;
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} else {
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pd->config[MRDMODE] &= ~MRDMODE_INTR_CH0;
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}
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if (pd->config[ARTTIM23] & ARTTIM23_INTR_CH1) {
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pd->config[MRDMODE] |= MRDMODE_INTR_CH1;
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} else {
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pd->config[MRDMODE] &= ~MRDMODE_INTR_CH1;
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}
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}
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static uint64_t bmdma_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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BMDMAState *bm = opaque;
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PCIDevice *pci_dev = PCI_DEVICE(bm->pci_dev);
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uint32_t val;
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if (size != 1) {
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return ((uint64_t)1 << (size * 8)) - 1;
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}
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switch(addr & 3) {
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case 0:
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val = bm->cmd;
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break;
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case 1:
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val = pci_dev->config[MRDMODE];
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break;
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case 2:
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val = bm->status;
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break;
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case 3:
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if (bm == &bm->pci_dev->bmdma[0]) {
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val = pci_dev->config[UDIDETCR0];
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} else {
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val = pci_dev->config[UDIDETCR1];
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}
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break;
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default:
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val = 0xff;
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break;
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}
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trace_bmdma_read_cmd646(addr, val);
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return val;
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}
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static void bmdma_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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BMDMAState *bm = opaque;
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PCIDevice *pci_dev = PCI_DEVICE(bm->pci_dev);
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if (size != 1) {
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return;
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}
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trace_bmdma_write_cmd646(addr, val);
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switch(addr & 3) {
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case 0:
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bmdma_cmd_writeb(bm, val);
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break;
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case 1:
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pci_dev->config[MRDMODE] =
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(pci_dev->config[MRDMODE] & ~0x30) | (val & 0x30);
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cmd646_update_dma_interrupts(pci_dev);
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cmd646_update_irq(pci_dev);
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break;
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case 2:
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bmdma_status_writeb(bm, val);
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break;
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case 3:
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if (bm == &bm->pci_dev->bmdma[0]) {
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pci_dev->config[UDIDETCR0] = val;
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} else {
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pci_dev->config[UDIDETCR1] = val;
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}
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break;
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}
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}
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static const MemoryRegionOps cmd646_bmdma_ops = {
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.read = bmdma_read,
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.write = bmdma_write,
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};
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static void bmdma_setup_bar(PCIIDEState *d)
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{
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BMDMAState *bm;
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int i;
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memory_region_init(&d->bmdma_bar, OBJECT(d), "cmd646-bmdma", 16);
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for(i = 0;i < 2; i++) {
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bm = &d->bmdma[i];
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memory_region_init_io(&bm->extra_io, OBJECT(d), &cmd646_bmdma_ops, bm,
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"cmd646-bmdma-bus", 4);
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memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io);
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memory_region_init_io(&bm->addr_ioport, OBJECT(d),
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&bmdma_addr_ioport_ops, bm,
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"cmd646-bmdma-ioport", 4);
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memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport);
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}
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}
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static void cmd646_update_irq(PCIDevice *pd)
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{
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int pci_level;
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pci_level = ((pd->config[MRDMODE] & MRDMODE_INTR_CH0) &&
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!(pd->config[MRDMODE] & MRDMODE_BLK_CH0)) ||
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((pd->config[MRDMODE] & MRDMODE_INTR_CH1) &&
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!(pd->config[MRDMODE] & MRDMODE_BLK_CH1));
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pci_set_irq(pd, pci_level);
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}
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/* the PCI irq level is the logical OR of the two channels */
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static void cmd646_set_irq(void *opaque, int channel, int level)
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{
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PCIIDEState *d = opaque;
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PCIDevice *pd = PCI_DEVICE(d);
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int irq_mask;
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irq_mask = MRDMODE_INTR_CH0 << channel;
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if (level) {
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pd->config[MRDMODE] |= irq_mask;
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} else {
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pd->config[MRDMODE] &= ~irq_mask;
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}
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cmd646_update_dma_interrupts(pd);
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cmd646_update_irq(pd);
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}
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static void cmd646_reset(DeviceState *dev)
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{
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PCIIDEState *d = PCI_IDE(dev);
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unsigned int i;
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for (i = 0; i < 2; i++) {
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ide_bus_reset(&d->bus[i]);
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}
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}
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static uint32_t cmd646_pci_config_read(PCIDevice *d,
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uint32_t address, int len)
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{
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return pci_default_read_config(d, address, len);
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}
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static void cmd646_pci_config_write(PCIDevice *d, uint32_t addr, uint32_t val,
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int l)
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{
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uint32_t i;
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pci_default_write_config(d, addr, val, l);
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for (i = addr; i < addr + l; i++) {
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switch (i) {
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case CFR:
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case ARTTIM23:
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cmd646_update_udma_interrupts(d);
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break;
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case MRDMODE:
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cmd646_update_dma_interrupts(d);
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break;
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}
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}
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cmd646_update_irq(d);
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}
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/* CMD646 PCI IDE controller */
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static void pci_cmd646_ide_realize(PCIDevice *dev, Error **errp)
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{
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PCIIDEState *d = PCI_IDE(dev);
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DeviceState *ds = DEVICE(dev);
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uint8_t *pci_conf = dev->config;
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int i;
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pci_conf[PCI_CLASS_PROG] = 0x8f;
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pci_conf[CNTRL] = CNTRL_EN_CH0; // enable IDE0
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if (d->secondary) {
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/* XXX: if not enabled, really disable the secondary IDE controller */
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pci_conf[CNTRL] |= CNTRL_EN_CH1; /* enable IDE1 */
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}
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/* Set write-to-clear interrupt bits */
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dev->wmask[CFR] = 0x0;
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dev->w1cmask[CFR] = CFR_INTR_CH0;
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dev->wmask[ARTTIM23] = 0x0;
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dev->w1cmask[ARTTIM23] = ARTTIM23_INTR_CH1;
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dev->wmask[MRDMODE] = 0x0;
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dev->w1cmask[MRDMODE] = MRDMODE_INTR_CH0 | MRDMODE_INTR_CH1;
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memory_region_init_io(&d->data_bar[0], OBJECT(d), &pci_ide_data_le_ops,
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&d->bus[0], "cmd646-data0", 8);
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pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->data_bar[0]);
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memory_region_init_io(&d->cmd_bar[0], OBJECT(d), &pci_ide_cmd_le_ops,
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&d->bus[0], "cmd646-cmd0", 4);
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pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd_bar[0]);
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memory_region_init_io(&d->data_bar[1], OBJECT(d), &pci_ide_data_le_ops,
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&d->bus[1], "cmd646-data1", 8);
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pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_IO, &d->data_bar[1]);
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memory_region_init_io(&d->cmd_bar[1], OBJECT(d), &pci_ide_cmd_le_ops,
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&d->bus[1], "cmd646-cmd1", 4);
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pci_register_bar(dev, 3, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd_bar[1]);
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bmdma_setup_bar(d);
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pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar);
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/* TODO: RST# value should be 0 */
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pci_conf[PCI_INTERRUPT_PIN] = 0x01; // interrupt on pin 1
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qdev_init_gpio_in(ds, cmd646_set_irq, 2);
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for (i = 0; i < 2; i++) {
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ide_bus_init(&d->bus[i], sizeof(d->bus[i]), ds, i, 2);
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ide_bus_init_output_irq(&d->bus[i], qdev_get_gpio_in(ds, i));
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bmdma_init(&d->bus[i], &d->bmdma[i], d);
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ide_bus_register_restart_cb(&d->bus[i]);
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}
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}
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static void pci_cmd646_ide_exitfn(PCIDevice *dev)
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{
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PCIIDEState *d = PCI_IDE(dev);
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unsigned i;
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for (i = 0; i < 2; ++i) {
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memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io);
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memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport);
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}
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}
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static Property cmd646_ide_properties[] = {
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DEFINE_PROP_UINT32("secondary", PCIIDEState, secondary, 0),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void cmd646_ide_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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device_class_set_legacy_reset(dc, cmd646_reset);
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dc->vmsd = &vmstate_ide_pci;
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k->realize = pci_cmd646_ide_realize;
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k->exit = pci_cmd646_ide_exitfn;
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k->vendor_id = PCI_VENDOR_ID_CMD;
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k->device_id = PCI_DEVICE_ID_CMD_646;
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k->revision = 0x07;
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k->class_id = PCI_CLASS_STORAGE_IDE;
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k->config_read = cmd646_pci_config_read;
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k->config_write = cmd646_pci_config_write;
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device_class_set_props(dc, cmd646_ide_properties);
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set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
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}
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static const TypeInfo cmd646_ide_info = {
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.name = "cmd646-ide",
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.parent = TYPE_PCI_IDE,
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.class_init = cmd646_ide_class_init,
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};
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static void cmd646_ide_register_types(void)
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{
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type_register_static(&cmd646_ide_info);
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}
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type_init(cmd646_ide_register_types)
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