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929 lines
32 KiB
C
929 lines
32 KiB
C
/*
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* ARM SBSA Reference Platform emulation
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*
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* Copyright (c) 2018 Linaro Limited
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* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
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* Written by Hongbo Zhang <hongbo.zhang@linaro.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/datadir.h"
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#include "qapi/error.h"
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#include "qemu/error-report.h"
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#include "qemu/units.h"
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#include "sysemu/device_tree.h"
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#include "sysemu/kvm.h"
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#include "sysemu/numa.h"
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#include "sysemu/runstate.h"
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#include "sysemu/sysemu.h"
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#include "exec/hwaddr.h"
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#include "kvm_arm.h"
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#include "hw/arm/boot.h"
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#include "hw/arm/bsa.h"
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#include "hw/arm/fdt.h"
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#include "hw/arm/smmuv3.h"
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#include "hw/block/flash.h"
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#include "hw/boards.h"
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#include "hw/ide/ide-bus.h"
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#include "hw/ide/ahci-sysbus.h"
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#include "hw/intc/arm_gicv3_common.h"
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#include "hw/intc/arm_gicv3_its_common.h"
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#include "hw/loader.h"
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#include "hw/pci-host/gpex.h"
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#include "hw/qdev-properties.h"
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#include "hw/usb.h"
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#include "hw/usb/xhci.h"
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#include "hw/char/pl011.h"
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#include "hw/watchdog/sbsa_gwdt.h"
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#include "net/net.h"
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#include "qapi/qmp/qlist.h"
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#include "qom/object.h"
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#include "target/arm/cpu-qom.h"
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#include "target/arm/gtimer.h"
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#define RAMLIMIT_GB 8192
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#define RAMLIMIT_BYTES (RAMLIMIT_GB * GiB)
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#define NUM_IRQS 256
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#define NUM_SMMU_IRQS 4
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#define NUM_SATA_PORTS 6
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/*
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* Generic timer frequency in Hz (which drives both the CPU generic timers
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* and the SBSA watchdog-timer). Older (<2.11) versions of the TF-A firmware
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* assumed 62.5MHz here.
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*
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* Starting with Armv8.6 CPU 1GHz timer frequency is mandated.
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*/
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#define SBSA_GTIMER_HZ 1000000000
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enum {
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SBSA_FLASH,
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SBSA_MEM,
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SBSA_CPUPERIPHS,
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SBSA_GIC_DIST,
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SBSA_GIC_REDIST,
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SBSA_GIC_ITS,
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SBSA_SECURE_EC,
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SBSA_GWDT_WS0,
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SBSA_GWDT_REFRESH,
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SBSA_GWDT_CONTROL,
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SBSA_SMMU,
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SBSA_UART,
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SBSA_RTC,
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SBSA_PCIE,
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SBSA_PCIE_MMIO,
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SBSA_PCIE_MMIO_HIGH,
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SBSA_PCIE_PIO,
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SBSA_PCIE_ECAM,
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SBSA_GPIO,
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SBSA_SECURE_UART,
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SBSA_SECURE_UART_MM,
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SBSA_SECURE_MEM,
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SBSA_AHCI,
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SBSA_XHCI,
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};
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struct SBSAMachineState {
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MachineState parent;
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struct arm_boot_info bootinfo;
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int smp_cpus;
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void *fdt;
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int fdt_size;
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int psci_conduit;
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DeviceState *gic;
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PFlashCFI01 *flash[2];
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};
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#define TYPE_SBSA_MACHINE MACHINE_TYPE_NAME("sbsa-ref")
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OBJECT_DECLARE_SIMPLE_TYPE(SBSAMachineState, SBSA_MACHINE)
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static const MemMapEntry sbsa_ref_memmap[] = {
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/* 512M boot ROM */
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[SBSA_FLASH] = { 0, 0x20000000 },
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/* 512M secure memory */
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[SBSA_SECURE_MEM] = { 0x20000000, 0x20000000 },
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/* Space reserved for CPU peripheral devices */
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[SBSA_CPUPERIPHS] = { 0x40000000, 0x00040000 },
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[SBSA_GIC_DIST] = { 0x40060000, 0x00010000 },
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[SBSA_GIC_REDIST] = { 0x40080000, 0x04000000 },
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[SBSA_GIC_ITS] = { 0x44081000, 0x00020000 },
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[SBSA_SECURE_EC] = { 0x50000000, 0x00001000 },
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[SBSA_GWDT_REFRESH] = { 0x50010000, 0x00001000 },
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[SBSA_GWDT_CONTROL] = { 0x50011000, 0x00001000 },
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[SBSA_UART] = { 0x60000000, 0x00001000 },
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[SBSA_RTC] = { 0x60010000, 0x00001000 },
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[SBSA_GPIO] = { 0x60020000, 0x00001000 },
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[SBSA_SECURE_UART] = { 0x60030000, 0x00001000 },
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[SBSA_SECURE_UART_MM] = { 0x60040000, 0x00001000 },
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[SBSA_SMMU] = { 0x60050000, 0x00020000 },
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/* Space here reserved for more SMMUs */
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[SBSA_AHCI] = { 0x60100000, 0x00010000 },
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[SBSA_XHCI] = { 0x60110000, 0x00010000 },
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/* Space here reserved for other devices */
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[SBSA_PCIE_PIO] = { 0x7fff0000, 0x00010000 },
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/* 32-bit address PCIE MMIO space */
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[SBSA_PCIE_MMIO] = { 0x80000000, 0x70000000 },
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/* 256M PCIE ECAM space */
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[SBSA_PCIE_ECAM] = { 0xf0000000, 0x10000000 },
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/* ~1TB PCIE MMIO space (4GB to 1024GB boundary) */
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[SBSA_PCIE_MMIO_HIGH] = { 0x100000000ULL, 0xFF00000000ULL },
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[SBSA_MEM] = { 0x10000000000ULL, RAMLIMIT_BYTES },
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};
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static const int sbsa_ref_irqmap[] = {
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[SBSA_UART] = 1,
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[SBSA_RTC] = 2,
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[SBSA_PCIE] = 3, /* ... to 6 */
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[SBSA_GPIO] = 7,
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[SBSA_SECURE_UART] = 8,
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[SBSA_SECURE_UART_MM] = 9,
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[SBSA_AHCI] = 10,
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[SBSA_XHCI] = 11,
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[SBSA_SMMU] = 12, /* ... to 15 */
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[SBSA_GWDT_WS0] = 16,
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};
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static uint64_t sbsa_ref_cpu_mp_affinity(SBSAMachineState *sms, int idx)
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{
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uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER;
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return arm_build_mp_affinity(idx, clustersz);
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}
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static void sbsa_fdt_add_gic_node(SBSAMachineState *sms)
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{
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const char *intc_nodename = "/intc";
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const char *its_nodename = "/intc/its";
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qemu_fdt_add_subnode(sms->fdt, intc_nodename);
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qemu_fdt_setprop_sized_cells(sms->fdt, intc_nodename, "reg",
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2, sbsa_ref_memmap[SBSA_GIC_DIST].base,
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2, sbsa_ref_memmap[SBSA_GIC_DIST].size,
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2, sbsa_ref_memmap[SBSA_GIC_REDIST].base,
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2, sbsa_ref_memmap[SBSA_GIC_REDIST].size);
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qemu_fdt_add_subnode(sms->fdt, its_nodename);
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qemu_fdt_setprop_sized_cells(sms->fdt, its_nodename, "reg",
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2, sbsa_ref_memmap[SBSA_GIC_ITS].base,
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2, sbsa_ref_memmap[SBSA_GIC_ITS].size);
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}
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/*
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* Firmware on this machine only uses ACPI table to load OS, these limited
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* device tree nodes are just to let firmware know the info which varies from
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* command line parameters, so it is not necessary to be fully compatible
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* with the kernel CPU and NUMA binding rules.
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*/
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static void create_fdt(SBSAMachineState *sms)
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{
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void *fdt = create_device_tree(&sms->fdt_size);
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const MachineState *ms = MACHINE(sms);
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int nb_numa_nodes = ms->numa_state->num_nodes;
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int cpu;
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if (!fdt) {
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error_report("create_device_tree() failed");
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exit(1);
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}
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sms->fdt = fdt;
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qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,sbsa-ref");
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qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
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qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
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/*
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* This versioning scheme is for informing platform fw only. It is neither:
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* - A QEMU versioned machine type; a given version of QEMU will emulate
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* a given version of the platform.
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* - A reflection of level of SBSA (now SystemReady SR) support provided.
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*
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* machine-version-major: updated when changes breaking fw compatibility
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* are introduced.
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* machine-version-minor: updated when features are added that don't break
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* fw compatibility.
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*/
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qemu_fdt_setprop_cell(fdt, "/", "machine-version-major", 0);
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qemu_fdt_setprop_cell(fdt, "/", "machine-version-minor", 4);
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if (ms->numa_state->have_numa_distance) {
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int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t);
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uint32_t *matrix = g_malloc0(size);
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int idx, i, j;
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for (i = 0; i < nb_numa_nodes; i++) {
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for (j = 0; j < nb_numa_nodes; j++) {
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idx = (i * nb_numa_nodes + j) * 3;
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matrix[idx + 0] = cpu_to_be32(i);
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matrix[idx + 1] = cpu_to_be32(j);
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matrix[idx + 2] =
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cpu_to_be32(ms->numa_state->nodes[i].distance[j]);
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}
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}
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qemu_fdt_add_subnode(fdt, "/distance-map");
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qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix",
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matrix, size);
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g_free(matrix);
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}
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/*
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* From Documentation/devicetree/bindings/arm/cpus.yaml
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* On ARM v8 64-bit systems this property is required
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* and matches the MPIDR_EL1 register affinity bits.
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*
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* * If cpus node's #address-cells property is set to 2
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*
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* The first reg cell bits [7:0] must be set to
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* bits [39:32] of MPIDR_EL1.
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*
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* The second reg cell bits [23:0] must be set to
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* bits [23:0] of MPIDR_EL1.
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*/
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qemu_fdt_add_subnode(sms->fdt, "/cpus");
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qemu_fdt_setprop_cell(sms->fdt, "/cpus", "#address-cells", 2);
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qemu_fdt_setprop_cell(sms->fdt, "/cpus", "#size-cells", 0x0);
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for (cpu = sms->smp_cpus - 1; cpu >= 0; cpu--) {
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char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
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ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
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CPUState *cs = CPU(armcpu);
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uint64_t mpidr = sbsa_ref_cpu_mp_affinity(sms, cpu);
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qemu_fdt_add_subnode(sms->fdt, nodename);
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qemu_fdt_setprop_u64(sms->fdt, nodename, "reg", mpidr);
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if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) {
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qemu_fdt_setprop_cell(sms->fdt, nodename, "numa-node-id",
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ms->possible_cpus->cpus[cs->cpu_index].props.node_id);
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}
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g_free(nodename);
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}
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/* Add CPU topology description through fdt node topology. */
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qemu_fdt_add_subnode(sms->fdt, "/cpus/topology");
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qemu_fdt_setprop_cell(sms->fdt, "/cpus/topology", "sockets", ms->smp.sockets);
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qemu_fdt_setprop_cell(sms->fdt, "/cpus/topology", "clusters", ms->smp.clusters);
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qemu_fdt_setprop_cell(sms->fdt, "/cpus/topology", "cores", ms->smp.cores);
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qemu_fdt_setprop_cell(sms->fdt, "/cpus/topology", "threads", ms->smp.threads);
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sbsa_fdt_add_gic_node(sms);
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}
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#define SBSA_FLASH_SECTOR_SIZE (256 * KiB)
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static PFlashCFI01 *sbsa_flash_create1(SBSAMachineState *sms,
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const char *name,
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const char *alias_prop_name)
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{
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/*
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* Create a single flash device. We use the same parameters as
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* the flash devices on the Versatile Express board.
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*/
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DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01);
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qdev_prop_set_uint64(dev, "sector-length", SBSA_FLASH_SECTOR_SIZE);
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qdev_prop_set_uint8(dev, "width", 4);
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qdev_prop_set_uint8(dev, "device-width", 2);
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qdev_prop_set_bit(dev, "big-endian", false);
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qdev_prop_set_uint16(dev, "id0", 0x89);
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qdev_prop_set_uint16(dev, "id1", 0x18);
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qdev_prop_set_uint16(dev, "id2", 0x00);
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qdev_prop_set_uint16(dev, "id3", 0x00);
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qdev_prop_set_string(dev, "name", name);
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object_property_add_child(OBJECT(sms), name, OBJECT(dev));
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object_property_add_alias(OBJECT(sms), alias_prop_name,
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OBJECT(dev), "drive");
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return PFLASH_CFI01(dev);
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}
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static void sbsa_flash_create(SBSAMachineState *sms)
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{
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sms->flash[0] = sbsa_flash_create1(sms, "sbsa.flash0", "pflash0");
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sms->flash[1] = sbsa_flash_create1(sms, "sbsa.flash1", "pflash1");
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}
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static void sbsa_flash_map1(PFlashCFI01 *flash,
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hwaddr base, hwaddr size,
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MemoryRegion *sysmem)
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{
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DeviceState *dev = DEVICE(flash);
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assert(QEMU_IS_ALIGNED(size, SBSA_FLASH_SECTOR_SIZE));
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assert(size / SBSA_FLASH_SECTOR_SIZE <= UINT32_MAX);
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qdev_prop_set_uint32(dev, "num-blocks", size / SBSA_FLASH_SECTOR_SIZE);
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sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
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memory_region_add_subregion(sysmem, base,
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sysbus_mmio_get_region(SYS_BUS_DEVICE(dev),
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0));
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}
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static void sbsa_flash_map(SBSAMachineState *sms,
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MemoryRegion *sysmem,
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MemoryRegion *secure_sysmem)
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{
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/*
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* Map two flash devices to fill the SBSA_FLASH space in the memmap.
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* sysmem is the system memory space. secure_sysmem is the secure view
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* of the system, and the first flash device should be made visible only
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* there. The second flash device is visible to both secure and nonsecure.
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*/
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hwaddr flashsize = sbsa_ref_memmap[SBSA_FLASH].size / 2;
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hwaddr flashbase = sbsa_ref_memmap[SBSA_FLASH].base;
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sbsa_flash_map1(sms->flash[0], flashbase, flashsize,
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secure_sysmem);
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sbsa_flash_map1(sms->flash[1], flashbase + flashsize, flashsize,
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sysmem);
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}
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static bool sbsa_firmware_init(SBSAMachineState *sms,
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MemoryRegion *sysmem,
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MemoryRegion *secure_sysmem)
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{
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const char *bios_name;
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int i;
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BlockBackend *pflash_blk0;
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/* Map legacy -drive if=pflash to machine properties */
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for (i = 0; i < ARRAY_SIZE(sms->flash); i++) {
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pflash_cfi01_legacy_drive(sms->flash[i],
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drive_get(IF_PFLASH, 0, i));
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}
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sbsa_flash_map(sms, sysmem, secure_sysmem);
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pflash_blk0 = pflash_cfi01_get_blk(sms->flash[0]);
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bios_name = MACHINE(sms)->firmware;
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if (bios_name) {
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char *fname;
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MemoryRegion *mr;
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int image_size;
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if (pflash_blk0) {
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error_report("The contents of the first flash device may be "
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"specified with -bios or with -drive if=pflash... "
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"but you cannot use both options at once");
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exit(1);
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}
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/* Fall back to -bios */
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fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
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if (!fname) {
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error_report("Could not find ROM image '%s'", bios_name);
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exit(1);
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}
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mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(sms->flash[0]), 0);
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image_size = load_image_mr(fname, mr);
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g_free(fname);
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if (image_size < 0) {
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error_report("Could not load ROM image '%s'", bios_name);
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exit(1);
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}
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}
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return pflash_blk0 || bios_name;
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}
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static void create_secure_ram(SBSAMachineState *sms,
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MemoryRegion *secure_sysmem)
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{
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MemoryRegion *secram = g_new(MemoryRegion, 1);
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hwaddr base = sbsa_ref_memmap[SBSA_SECURE_MEM].base;
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hwaddr size = sbsa_ref_memmap[SBSA_SECURE_MEM].size;
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memory_region_init_ram(secram, NULL, "sbsa-ref.secure-ram", size,
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&error_fatal);
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memory_region_add_subregion(secure_sysmem, base, secram);
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}
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static void create_its(SBSAMachineState *sms)
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{
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const char *itsclass = its_class_name();
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DeviceState *dev;
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dev = qdev_new(itsclass);
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|
|
|
object_property_set_link(OBJECT(dev), "parent-gicv3", OBJECT(sms->gic),
|
|
&error_abort);
|
|
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, sbsa_ref_memmap[SBSA_GIC_ITS].base);
|
|
}
|
|
|
|
static void create_gic(SBSAMachineState *sms, MemoryRegion *mem)
|
|
{
|
|
unsigned int smp_cpus = MACHINE(sms)->smp.cpus;
|
|
SysBusDevice *gicbusdev;
|
|
const char *gictype;
|
|
uint32_t redist0_capacity, redist0_count;
|
|
QList *redist_region_count;
|
|
int i;
|
|
|
|
gictype = gicv3_class_name();
|
|
|
|
sms->gic = qdev_new(gictype);
|
|
qdev_prop_set_uint32(sms->gic, "revision", 3);
|
|
qdev_prop_set_uint32(sms->gic, "num-cpu", smp_cpus);
|
|
/*
|
|
* Note that the num-irq property counts both internal and external
|
|
* interrupts; there are always 32 of the former (mandated by GIC spec).
|
|
*/
|
|
qdev_prop_set_uint32(sms->gic, "num-irq", NUM_IRQS + 32);
|
|
qdev_prop_set_bit(sms->gic, "has-security-extensions", true);
|
|
|
|
redist0_capacity =
|
|
sbsa_ref_memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZE;
|
|
redist0_count = MIN(smp_cpus, redist0_capacity);
|
|
|
|
redist_region_count = qlist_new();
|
|
qlist_append_int(redist_region_count, redist0_count);
|
|
qdev_prop_set_array(sms->gic, "redist-region-count", redist_region_count);
|
|
|
|
object_property_set_link(OBJECT(sms->gic), "sysmem",
|
|
OBJECT(mem), &error_fatal);
|
|
qdev_prop_set_bit(sms->gic, "has-lpi", true);
|
|
|
|
gicbusdev = SYS_BUS_DEVICE(sms->gic);
|
|
sysbus_realize_and_unref(gicbusdev, &error_fatal);
|
|
sysbus_mmio_map(gicbusdev, 0, sbsa_ref_memmap[SBSA_GIC_DIST].base);
|
|
sysbus_mmio_map(gicbusdev, 1, sbsa_ref_memmap[SBSA_GIC_REDIST].base);
|
|
|
|
/*
|
|
* Wire the outputs from each CPU's generic timer and the GICv3
|
|
* maintenance interrupt signal to the appropriate GIC PPI inputs,
|
|
* and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
|
|
*/
|
|
for (i = 0; i < smp_cpus; i++) {
|
|
DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
|
|
int intidbase = NUM_IRQS + i * GIC_INTERNAL;
|
|
int irq;
|
|
/*
|
|
* Mapping from the output timer irq lines from the CPU to the
|
|
* GIC PPI inputs used for this board.
|
|
*/
|
|
const int timer_irq[] = {
|
|
[GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ,
|
|
[GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,
|
|
[GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ,
|
|
[GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ,
|
|
[GTIMER_HYPVIRT] = ARCH_TIMER_NS_EL2_VIRT_IRQ,
|
|
};
|
|
|
|
for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
|
|
qdev_connect_gpio_out(cpudev, irq,
|
|
qdev_get_gpio_in(sms->gic,
|
|
intidbase + timer_irq[irq]));
|
|
}
|
|
|
|
qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0,
|
|
qdev_get_gpio_in(sms->gic,
|
|
intidbase
|
|
+ ARCH_GIC_MAINT_IRQ));
|
|
|
|
qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0,
|
|
qdev_get_gpio_in(sms->gic,
|
|
intidbase
|
|
+ VIRTUAL_PMU_IRQ));
|
|
|
|
sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
|
|
sysbus_connect_irq(gicbusdev, i + smp_cpus,
|
|
qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
|
|
sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus,
|
|
qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
|
|
sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus,
|
|
qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
|
|
}
|
|
create_its(sms);
|
|
}
|
|
|
|
static void create_uart(const SBSAMachineState *sms, int uart,
|
|
MemoryRegion *mem, Chardev *chr)
|
|
{
|
|
hwaddr base = sbsa_ref_memmap[uart].base;
|
|
int irq = sbsa_ref_irqmap[uart];
|
|
DeviceState *dev = qdev_new(TYPE_PL011);
|
|
SysBusDevice *s = SYS_BUS_DEVICE(dev);
|
|
|
|
qdev_prop_set_chr(dev, "chardev", chr);
|
|
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
|
|
memory_region_add_subregion(mem, base,
|
|
sysbus_mmio_get_region(s, 0));
|
|
sysbus_connect_irq(s, 0, qdev_get_gpio_in(sms->gic, irq));
|
|
}
|
|
|
|
static void create_rtc(const SBSAMachineState *sms)
|
|
{
|
|
hwaddr base = sbsa_ref_memmap[SBSA_RTC].base;
|
|
int irq = sbsa_ref_irqmap[SBSA_RTC];
|
|
|
|
sysbus_create_simple("pl031", base, qdev_get_gpio_in(sms->gic, irq));
|
|
}
|
|
|
|
static void create_wdt(const SBSAMachineState *sms)
|
|
{
|
|
hwaddr rbase = sbsa_ref_memmap[SBSA_GWDT_REFRESH].base;
|
|
hwaddr cbase = sbsa_ref_memmap[SBSA_GWDT_CONTROL].base;
|
|
DeviceState *dev = qdev_new(TYPE_WDT_SBSA);
|
|
SysBusDevice *s = SYS_BUS_DEVICE(dev);
|
|
int irq = sbsa_ref_irqmap[SBSA_GWDT_WS0];
|
|
|
|
qdev_prop_set_uint64(dev, "clock-frequency", SBSA_GTIMER_HZ);
|
|
sysbus_realize_and_unref(s, &error_fatal);
|
|
sysbus_mmio_map(s, 0, rbase);
|
|
sysbus_mmio_map(s, 1, cbase);
|
|
sysbus_connect_irq(s, 0, qdev_get_gpio_in(sms->gic, irq));
|
|
}
|
|
|
|
static DeviceState *gpio_key_dev;
|
|
static void sbsa_ref_powerdown_req(Notifier *n, void *opaque)
|
|
{
|
|
/* use gpio Pin 3 for power button event */
|
|
qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1);
|
|
}
|
|
|
|
static Notifier sbsa_ref_powerdown_notifier = {
|
|
.notify = sbsa_ref_powerdown_req
|
|
};
|
|
|
|
static void create_gpio(const SBSAMachineState *sms)
|
|
{
|
|
DeviceState *pl061_dev;
|
|
hwaddr base = sbsa_ref_memmap[SBSA_GPIO].base;
|
|
int irq = sbsa_ref_irqmap[SBSA_GPIO];
|
|
|
|
pl061_dev = sysbus_create_simple("pl061", base,
|
|
qdev_get_gpio_in(sms->gic, irq));
|
|
|
|
gpio_key_dev = sysbus_create_simple("gpio-key", -1,
|
|
qdev_get_gpio_in(pl061_dev, 3));
|
|
|
|
/* connect powerdown request */
|
|
qemu_register_powerdown_notifier(&sbsa_ref_powerdown_notifier);
|
|
}
|
|
|
|
static void create_ahci(const SBSAMachineState *sms)
|
|
{
|
|
hwaddr base = sbsa_ref_memmap[SBSA_AHCI].base;
|
|
int irq = sbsa_ref_irqmap[SBSA_AHCI];
|
|
DeviceState *dev;
|
|
DriveInfo *hd[NUM_SATA_PORTS];
|
|
SysbusAHCIState *sysahci;
|
|
|
|
dev = qdev_new("sysbus-ahci");
|
|
qdev_prop_set_uint32(dev, "num-ports", NUM_SATA_PORTS);
|
|
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(sms->gic, irq));
|
|
|
|
sysahci = SYSBUS_AHCI(dev);
|
|
ide_drive_get(hd, ARRAY_SIZE(hd));
|
|
ahci_ide_create_devs(&sysahci->ahci, hd);
|
|
}
|
|
|
|
static void create_xhci(const SBSAMachineState *sms)
|
|
{
|
|
hwaddr base = sbsa_ref_memmap[SBSA_XHCI].base;
|
|
int irq = sbsa_ref_irqmap[SBSA_XHCI];
|
|
DeviceState *dev = qdev_new(TYPE_XHCI_SYSBUS);
|
|
qdev_prop_set_uint32(dev, "slots", XHCI_MAXSLOTS);
|
|
|
|
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(sms->gic, irq));
|
|
}
|
|
|
|
static void create_smmu(const SBSAMachineState *sms, PCIBus *bus)
|
|
{
|
|
hwaddr base = sbsa_ref_memmap[SBSA_SMMU].base;
|
|
int irq = sbsa_ref_irqmap[SBSA_SMMU];
|
|
DeviceState *dev;
|
|
int i;
|
|
|
|
dev = qdev_new(TYPE_ARM_SMMUV3);
|
|
|
|
object_property_set_str(OBJECT(dev), "stage", "nested", &error_abort);
|
|
object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus),
|
|
&error_abort);
|
|
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
|
|
for (i = 0; i < NUM_SMMU_IRQS; i++) {
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
|
|
qdev_get_gpio_in(sms->gic, irq + i));
|
|
}
|
|
}
|
|
|
|
static void create_pcie(SBSAMachineState *sms)
|
|
{
|
|
hwaddr base_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].base;
|
|
hwaddr size_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].size;
|
|
hwaddr base_mmio = sbsa_ref_memmap[SBSA_PCIE_MMIO].base;
|
|
hwaddr size_mmio = sbsa_ref_memmap[SBSA_PCIE_MMIO].size;
|
|
hwaddr base_mmio_high = sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].base;
|
|
hwaddr size_mmio_high = sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].size;
|
|
hwaddr base_pio = sbsa_ref_memmap[SBSA_PCIE_PIO].base;
|
|
int irq = sbsa_ref_irqmap[SBSA_PCIE];
|
|
MachineClass *mc = MACHINE_GET_CLASS(sms);
|
|
MemoryRegion *mmio_alias, *mmio_alias_high, *mmio_reg;
|
|
MemoryRegion *ecam_alias, *ecam_reg;
|
|
DeviceState *dev;
|
|
PCIHostState *pci;
|
|
int i;
|
|
|
|
dev = qdev_new(TYPE_GPEX_HOST);
|
|
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
|
|
|
|
/* Map ECAM space */
|
|
ecam_alias = g_new0(MemoryRegion, 1);
|
|
ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
|
|
memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
|
|
ecam_reg, 0, size_ecam);
|
|
memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias);
|
|
|
|
/* Map the MMIO space */
|
|
mmio_alias = g_new0(MemoryRegion, 1);
|
|
mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
|
|
memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio",
|
|
mmio_reg, base_mmio, size_mmio);
|
|
memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias);
|
|
|
|
/* Map the MMIO_HIGH space */
|
|
mmio_alias_high = g_new0(MemoryRegion, 1);
|
|
memory_region_init_alias(mmio_alias_high, OBJECT(dev), "pcie-mmio-high",
|
|
mmio_reg, base_mmio_high, size_mmio_high);
|
|
memory_region_add_subregion(get_system_memory(), base_mmio_high,
|
|
mmio_alias_high);
|
|
|
|
/* Map IO port space */
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio);
|
|
|
|
for (i = 0; i < GPEX_NUM_IRQS; i++) {
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
|
|
qdev_get_gpio_in(sms->gic, irq + i));
|
|
gpex_set_irq_num(GPEX_HOST(dev), i, irq + i);
|
|
}
|
|
|
|
pci = PCI_HOST_BRIDGE(dev);
|
|
|
|
pci_init_nic_devices(pci->bus, mc->default_nic);
|
|
|
|
pci_create_simple(pci->bus, -1, "bochs-display");
|
|
|
|
create_smmu(sms, pci->bus);
|
|
}
|
|
|
|
static void *sbsa_ref_dtb(const struct arm_boot_info *binfo, int *fdt_size)
|
|
{
|
|
const SBSAMachineState *board = container_of(binfo, SBSAMachineState,
|
|
bootinfo);
|
|
|
|
*fdt_size = board->fdt_size;
|
|
return board->fdt;
|
|
}
|
|
|
|
static void create_secure_ec(MemoryRegion *mem)
|
|
{
|
|
hwaddr base = sbsa_ref_memmap[SBSA_SECURE_EC].base;
|
|
DeviceState *dev = qdev_new("sbsa-ec");
|
|
SysBusDevice *s = SYS_BUS_DEVICE(dev);
|
|
|
|
memory_region_add_subregion(mem, base,
|
|
sysbus_mmio_get_region(s, 0));
|
|
}
|
|
|
|
static void sbsa_ref_init(MachineState *machine)
|
|
{
|
|
unsigned int smp_cpus = machine->smp.cpus;
|
|
unsigned int max_cpus = machine->smp.max_cpus;
|
|
SBSAMachineState *sms = SBSA_MACHINE(machine);
|
|
MachineClass *mc = MACHINE_GET_CLASS(machine);
|
|
MemoryRegion *sysmem = get_system_memory();
|
|
MemoryRegion *secure_sysmem = g_new(MemoryRegion, 1);
|
|
bool firmware_loaded;
|
|
const CPUArchIdList *possible_cpus;
|
|
int n, sbsa_max_cpus;
|
|
|
|
if (kvm_enabled()) {
|
|
error_report("sbsa-ref: KVM is not supported for this machine");
|
|
exit(1);
|
|
}
|
|
|
|
/*
|
|
* The Secure view of the world is the same as the NonSecure,
|
|
* but with a few extra devices. Create it as a container region
|
|
* containing the system memory at low priority; any secure-only
|
|
* devices go in at higher priority and take precedence.
|
|
*/
|
|
memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory",
|
|
UINT64_MAX);
|
|
memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1);
|
|
|
|
firmware_loaded = sbsa_firmware_init(sms, sysmem, secure_sysmem);
|
|
|
|
/*
|
|
* This machine has EL3 enabled, external firmware should supply PSCI
|
|
* implementation, so the QEMU's internal PSCI is disabled.
|
|
*/
|
|
sms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED;
|
|
|
|
sbsa_max_cpus = sbsa_ref_memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZE;
|
|
|
|
if (max_cpus > sbsa_max_cpus) {
|
|
error_report("Number of SMP CPUs requested (%d) exceeds max CPUs "
|
|
"supported by machine 'sbsa-ref' (%d)",
|
|
max_cpus, sbsa_max_cpus);
|
|
exit(1);
|
|
}
|
|
|
|
sms->smp_cpus = smp_cpus;
|
|
|
|
if (machine->ram_size > sbsa_ref_memmap[SBSA_MEM].size) {
|
|
error_report("sbsa-ref: cannot model more than %dGB RAM", RAMLIMIT_GB);
|
|
exit(1);
|
|
}
|
|
|
|
possible_cpus = mc->possible_cpu_arch_ids(machine);
|
|
for (n = 0; n < possible_cpus->len; n++) {
|
|
Object *cpuobj;
|
|
CPUState *cs;
|
|
|
|
if (n >= smp_cpus) {
|
|
break;
|
|
}
|
|
|
|
cpuobj = object_new(possible_cpus->cpus[n].type);
|
|
object_property_set_int(cpuobj, "mp-affinity",
|
|
possible_cpus->cpus[n].arch_id, NULL);
|
|
|
|
cs = CPU(cpuobj);
|
|
cs->cpu_index = n;
|
|
|
|
numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj),
|
|
&error_fatal);
|
|
|
|
if (object_property_find(cpuobj, "reset-cbar")) {
|
|
object_property_set_int(cpuobj, "reset-cbar",
|
|
sbsa_ref_memmap[SBSA_CPUPERIPHS].base,
|
|
&error_abort);
|
|
}
|
|
|
|
object_property_set_int(cpuobj, "cntfrq", SBSA_GTIMER_HZ, &error_abort);
|
|
|
|
object_property_set_link(cpuobj, "memory", OBJECT(sysmem),
|
|
&error_abort);
|
|
|
|
object_property_set_link(cpuobj, "secure-memory",
|
|
OBJECT(secure_sysmem), &error_abort);
|
|
|
|
qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
|
|
object_unref(cpuobj);
|
|
}
|
|
|
|
memory_region_add_subregion(sysmem, sbsa_ref_memmap[SBSA_MEM].base,
|
|
machine->ram);
|
|
|
|
create_fdt(sms);
|
|
|
|
create_secure_ram(sms, secure_sysmem);
|
|
|
|
create_gic(sms, sysmem);
|
|
|
|
create_uart(sms, SBSA_UART, sysmem, serial_hd(0));
|
|
create_uart(sms, SBSA_SECURE_UART, secure_sysmem, serial_hd(1));
|
|
/* Second secure UART for RAS and MM from EL0 */
|
|
create_uart(sms, SBSA_SECURE_UART_MM, secure_sysmem, serial_hd(2));
|
|
|
|
create_rtc(sms);
|
|
|
|
create_wdt(sms);
|
|
|
|
create_gpio(sms);
|
|
|
|
create_ahci(sms);
|
|
|
|
create_xhci(sms);
|
|
|
|
create_pcie(sms);
|
|
|
|
create_secure_ec(secure_sysmem);
|
|
|
|
sms->bootinfo.ram_size = machine->ram_size;
|
|
sms->bootinfo.board_id = -1;
|
|
sms->bootinfo.loader_start = sbsa_ref_memmap[SBSA_MEM].base;
|
|
sms->bootinfo.get_dtb = sbsa_ref_dtb;
|
|
sms->bootinfo.firmware_loaded = firmware_loaded;
|
|
arm_load_kernel(ARM_CPU(first_cpu), machine, &sms->bootinfo);
|
|
}
|
|
|
|
static const CPUArchIdList *sbsa_ref_possible_cpu_arch_ids(MachineState *ms)
|
|
{
|
|
unsigned int max_cpus = ms->smp.max_cpus;
|
|
SBSAMachineState *sms = SBSA_MACHINE(ms);
|
|
int n;
|
|
|
|
if (ms->possible_cpus) {
|
|
assert(ms->possible_cpus->len == max_cpus);
|
|
return ms->possible_cpus;
|
|
}
|
|
|
|
ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
|
|
sizeof(CPUArchId) * max_cpus);
|
|
ms->possible_cpus->len = max_cpus;
|
|
for (n = 0; n < ms->possible_cpus->len; n++) {
|
|
ms->possible_cpus->cpus[n].type = ms->cpu_type;
|
|
ms->possible_cpus->cpus[n].arch_id =
|
|
sbsa_ref_cpu_mp_affinity(sms, n);
|
|
ms->possible_cpus->cpus[n].props.has_thread_id = true;
|
|
ms->possible_cpus->cpus[n].props.thread_id = n;
|
|
}
|
|
return ms->possible_cpus;
|
|
}
|
|
|
|
static CpuInstanceProperties
|
|
sbsa_ref_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
|
|
{
|
|
MachineClass *mc = MACHINE_GET_CLASS(ms);
|
|
const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms);
|
|
|
|
assert(cpu_index < possible_cpus->len);
|
|
return possible_cpus->cpus[cpu_index].props;
|
|
}
|
|
|
|
static int64_t
|
|
sbsa_ref_get_default_cpu_node_id(const MachineState *ms, int idx)
|
|
{
|
|
return idx % ms->numa_state->num_nodes;
|
|
}
|
|
|
|
static void sbsa_ref_instance_init(Object *obj)
|
|
{
|
|
SBSAMachineState *sms = SBSA_MACHINE(obj);
|
|
|
|
sbsa_flash_create(sms);
|
|
}
|
|
|
|
static void sbsa_ref_class_init(ObjectClass *oc, void *data)
|
|
{
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
static const char * const valid_cpu_types[] = {
|
|
ARM_CPU_TYPE_NAME("cortex-a57"),
|
|
ARM_CPU_TYPE_NAME("cortex-a72"),
|
|
ARM_CPU_TYPE_NAME("neoverse-n1"),
|
|
ARM_CPU_TYPE_NAME("neoverse-v1"),
|
|
ARM_CPU_TYPE_NAME("neoverse-n2"),
|
|
ARM_CPU_TYPE_NAME("max"),
|
|
NULL,
|
|
};
|
|
|
|
mc->init = sbsa_ref_init;
|
|
mc->desc = "QEMU 'SBSA Reference' ARM Virtual Machine";
|
|
mc->default_cpu_type = ARM_CPU_TYPE_NAME("neoverse-n2");
|
|
mc->valid_cpu_types = valid_cpu_types;
|
|
mc->max_cpus = 512;
|
|
mc->pci_allow_0_address = true;
|
|
mc->minimum_page_bits = 12;
|
|
mc->block_default_type = IF_IDE;
|
|
mc->no_cdrom = 1;
|
|
mc->default_nic = "e1000e";
|
|
mc->default_ram_size = 1 * GiB;
|
|
mc->default_ram_id = "sbsa-ref.ram";
|
|
mc->default_cpus = 4;
|
|
mc->smp_props.clusters_supported = true;
|
|
mc->possible_cpu_arch_ids = sbsa_ref_possible_cpu_arch_ids;
|
|
mc->cpu_index_to_instance_props = sbsa_ref_cpu_index_to_props;
|
|
mc->get_default_cpu_node_id = sbsa_ref_get_default_cpu_node_id;
|
|
/* platform instead of architectural choice */
|
|
mc->cpu_cluster_has_numa_boundary = true;
|
|
}
|
|
|
|
static const TypeInfo sbsa_ref_info = {
|
|
.name = TYPE_SBSA_MACHINE,
|
|
.parent = TYPE_MACHINE,
|
|
.instance_init = sbsa_ref_instance_init,
|
|
.class_init = sbsa_ref_class_init,
|
|
.instance_size = sizeof(SBSAMachineState),
|
|
};
|
|
|
|
static void sbsa_ref_machine_init(void)
|
|
{
|
|
type_register_static(&sbsa_ref_info);
|
|
}
|
|
|
|
type_init(sbsa_ref_machine_init);
|