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641 lines
24 KiB
C
641 lines
24 KiB
C
/*
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* Arm MPS3 board emulation for Cortex-R-based FPGA images.
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* (For M-profile images see mps2.c and mps2tz.c.)
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*
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* Copyright (c) 2017 Linaro Limited
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* Written by Peter Maydell
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 or
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* (at your option) any later version.
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*/
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/*
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* The MPS3 is an FPGA based dev board. This file handles FPGA images
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* which use the Cortex-R CPUs. We model these separately from the
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* M-profile images, because on M-profile the FPGA image is based on
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* a "Subsystem for Embedded" which is similar to an SoC, whereas
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* the R-profile FPGA images don't have that abstraction layer.
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*
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* We model the following FPGA images here:
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* "mps3-an536" -- dual Cortex-R52 as documented in Arm Application Note AN536
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*
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* Application Note AN536:
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* https://developer.arm.com/documentation/dai0536/latest/
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*/
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#include "qemu/osdep.h"
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#include "qemu/units.h"
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#include "qapi/error.h"
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#include "qapi/qmp/qlist.h"
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#include "exec/address-spaces.h"
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#include "cpu.h"
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#include "sysemu/sysemu.h"
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#include "hw/boards.h"
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#include "hw/or-irq.h"
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#include "hw/qdev-clock.h"
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#include "hw/qdev-properties.h"
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#include "hw/arm/boot.h"
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#include "hw/arm/bsa.h"
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#include "hw/char/cmsdk-apb-uart.h"
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#include "hw/i2c/arm_sbcon_i2c.h"
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#include "hw/intc/arm_gicv3.h"
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#include "hw/misc/mps2-scc.h"
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#include "hw/misc/mps2-fpgaio.h"
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#include "hw/misc/unimp.h"
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#include "hw/net/lan9118.h"
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#include "hw/rtc/pl031.h"
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#include "hw/ssi/pl022.h"
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#include "hw/timer/cmsdk-apb-dualtimer.h"
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#include "hw/watchdog/cmsdk-apb-watchdog.h"
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/* Define the layout of RAM and ROM in a board */
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typedef struct RAMInfo {
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const char *name;
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hwaddr base;
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hwaddr size;
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int mrindex; /* index into rams[]; -1 for the system RAM block */
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int flags;
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} RAMInfo;
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/*
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* The MPS3 DDR is 3GiB, but on a 32-bit host QEMU doesn't permit
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* emulation of that much guest RAM, so artificially make it smaller.
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*/
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#if HOST_LONG_BITS == 32
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#define MPS3_DDR_SIZE (1 * GiB)
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#else
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#define MPS3_DDR_SIZE (3 * GiB)
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#endif
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/*
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* Flag values:
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* IS_MAIN: this is the main machine RAM
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* IS_ROM: this area is read-only
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*/
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#define IS_MAIN 1
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#define IS_ROM 2
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#define MPS3R_RAM_MAX 9
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#define MPS3R_CPU_MAX 2
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#define MPS3R_UART_MAX 4 /* shared UART count */
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#define PERIPHBASE 0xf0000000
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#define NUM_SPIS 96
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typedef enum MPS3RFPGAType {
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FPGA_AN536,
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} MPS3RFPGAType;
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struct MPS3RMachineClass {
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MachineClass parent;
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MPS3RFPGAType fpga_type;
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const RAMInfo *raminfo;
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hwaddr loader_start;
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};
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struct MPS3RMachineState {
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MachineState parent;
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struct arm_boot_info bootinfo;
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MemoryRegion ram[MPS3R_RAM_MAX];
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Object *cpu[MPS3R_CPU_MAX];
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MemoryRegion cpu_sysmem[MPS3R_CPU_MAX];
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MemoryRegion sysmem_alias[MPS3R_CPU_MAX];
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MemoryRegion cpu_ram[MPS3R_CPU_MAX];
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GICv3State gic;
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/* per-CPU UARTs followed by the shared UARTs */
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CMSDKAPBUART uart[MPS3R_CPU_MAX + MPS3R_UART_MAX];
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OrIRQState cpu_uart_oflow[MPS3R_CPU_MAX];
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OrIRQState uart_oflow;
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CMSDKAPBWatchdog watchdog;
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CMSDKAPBDualTimer dualtimer;
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ArmSbconI2CState i2c[5];
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PL022State spi[3];
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MPS2SCC scc;
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MPS2FPGAIO fpgaio;
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UnimplementedDeviceState i2s_audio;
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PL031State rtc;
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Clock *clk;
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};
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#define TYPE_MPS3R_MACHINE "mps3r"
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#define TYPE_MPS3R_AN536_MACHINE MACHINE_TYPE_NAME("mps3-an536")
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OBJECT_DECLARE_TYPE(MPS3RMachineState, MPS3RMachineClass, MPS3R_MACHINE)
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/*
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* Main clock frequency CLK in Hz (50MHz). In the image there are also
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* ACLK, MCLK, GPUCLK and PERIPHCLK at the same frequency; for our
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* model we just roll them all into one.
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*/
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#define CLK_FRQ 50000000
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static const RAMInfo an536_raminfo[] = {
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{
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.name = "ATCM",
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.base = 0x00000000,
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.size = 0x00008000,
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.mrindex = 0,
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}, {
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/* We model the QSPI flash as simple ROM for now */
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.name = "QSPI",
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.base = 0x08000000,
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.size = 0x00800000,
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.flags = IS_ROM,
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.mrindex = 1,
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}, {
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.name = "BRAM",
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.base = 0x10000000,
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.size = 0x00080000,
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.mrindex = 2,
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}, {
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.name = "DDR",
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.base = 0x20000000,
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.size = MPS3_DDR_SIZE,
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.mrindex = -1,
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}, {
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.name = "ATCM0",
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.base = 0xee000000,
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.size = 0x00008000,
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.mrindex = 3,
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}, {
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.name = "BTCM0",
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.base = 0xee100000,
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.size = 0x00008000,
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.mrindex = 4,
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}, {
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.name = "CTCM0",
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.base = 0xee200000,
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.size = 0x00008000,
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.mrindex = 5,
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}, {
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.name = "ATCM1",
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.base = 0xee400000,
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.size = 0x00008000,
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.mrindex = 6,
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}, {
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.name = "BTCM1",
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.base = 0xee500000,
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.size = 0x00008000,
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.mrindex = 7,
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}, {
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.name = "CTCM1",
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.base = 0xee600000,
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.size = 0x00008000,
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.mrindex = 8,
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}, {
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.name = NULL,
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}
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};
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static const int an536_oscclk[] = {
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24000000, /* 24MHz reference for RTC and timers */
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50000000, /* 50MHz ACLK */
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50000000, /* 50MHz MCLK */
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50000000, /* 50MHz GPUCLK */
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24576000, /* 24.576MHz AUDCLK */
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23750000, /* 23.75MHz HDLCDCLK */
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100000000, /* 100MHz DDR4_REF_CLK */
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};
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static MemoryRegion *mr_for_raminfo(MPS3RMachineState *mms,
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const RAMInfo *raminfo)
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{
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/* Return an initialized MemoryRegion for the RAMInfo. */
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MemoryRegion *ram;
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if (raminfo->mrindex < 0) {
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/* Means this RAMInfo is for QEMU's "system memory" */
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MachineState *machine = MACHINE(mms);
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assert(!(raminfo->flags & IS_ROM));
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return machine->ram;
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}
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assert(raminfo->mrindex < MPS3R_RAM_MAX);
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ram = &mms->ram[raminfo->mrindex];
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memory_region_init_ram(ram, NULL, raminfo->name,
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raminfo->size, &error_fatal);
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if (raminfo->flags & IS_ROM) {
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memory_region_set_readonly(ram, true);
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}
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return ram;
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}
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/*
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* There is no defined secondary boot protocol for Linux for the AN536,
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* because real hardware has a restriction that atomic operations between
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* the two CPUs do not function correctly, and so true SMP is not
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* possible. Therefore for cases where the user is directly booting
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* a kernel, we treat the system as essentially uniprocessor, and
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* put the secondary CPU into power-off state (as if the user on the
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* real hardware had configured the secondary to be halted via the
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* SCC config registers).
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*
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* Note that the default secondary boot code would not work here anyway
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* as it assumes a GICv2, and we have a GICv3.
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*/
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static void mps3r_write_secondary_boot(ARMCPU *cpu,
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const struct arm_boot_info *info)
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{
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/*
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* Power the secondary CPU off. This means we don't need to write any
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* boot code into guest memory. Note that the 'cpu' argument to this
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* function is the primary CPU we passed to arm_load_kernel(), not
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* the secondary. Loop around all the other CPUs, as the boot.c
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* code does for the "disable secondaries if PSCI is enabled" case.
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*/
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for (CPUState *cs = first_cpu; cs; cs = CPU_NEXT(cs)) {
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if (cs != first_cpu) {
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object_property_set_bool(OBJECT(cs), "start-powered-off", true,
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&error_abort);
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}
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}
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}
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static void mps3r_secondary_cpu_reset(ARMCPU *cpu,
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const struct arm_boot_info *info)
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{
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/* We don't need to do anything here because the CPU will be off */
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}
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static void create_gic(MPS3RMachineState *mms, MemoryRegion *sysmem)
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{
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MachineState *machine = MACHINE(mms);
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DeviceState *gicdev;
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QList *redist_region_count;
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object_initialize_child(OBJECT(mms), "gic", &mms->gic, TYPE_ARM_GICV3);
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gicdev = DEVICE(&mms->gic);
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qdev_prop_set_uint32(gicdev, "num-cpu", machine->smp.cpus);
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qdev_prop_set_uint32(gicdev, "num-irq", NUM_SPIS + GIC_INTERNAL);
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redist_region_count = qlist_new();
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qlist_append_int(redist_region_count, machine->smp.cpus);
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qdev_prop_set_array(gicdev, "redist-region-count", redist_region_count);
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object_property_set_link(OBJECT(&mms->gic), "sysmem",
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OBJECT(sysmem), &error_fatal);
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sysbus_realize(SYS_BUS_DEVICE(&mms->gic), &error_fatal);
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sysbus_mmio_map(SYS_BUS_DEVICE(&mms->gic), 0, PERIPHBASE);
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sysbus_mmio_map(SYS_BUS_DEVICE(&mms->gic), 1, PERIPHBASE + 0x100000);
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/*
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* Wire the outputs from each CPU's generic timer and the GICv3
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* maintenance interrupt signal to the appropriate GIC PPI inputs,
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* and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
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*/
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for (int i = 0; i < machine->smp.cpus; i++) {
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DeviceState *cpudev = DEVICE(mms->cpu[i]);
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SysBusDevice *gicsbd = SYS_BUS_DEVICE(&mms->gic);
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int intidbase = NUM_SPIS + i * GIC_INTERNAL;
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int irq;
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/*
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* Mapping from the output timer irq lines from the CPU to the
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* GIC PPI inputs used for this board. This isn't a BSA board,
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* but it uses the standard convention for the PPI numbers.
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*/
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const int timer_irq[] = {
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[GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ,
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[GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,
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[GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ,
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};
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for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
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qdev_connect_gpio_out(cpudev, irq,
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qdev_get_gpio_in(gicdev,
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intidbase + timer_irq[irq]));
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}
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qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0,
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qdev_get_gpio_in(gicdev,
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intidbase + ARCH_GIC_MAINT_IRQ));
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qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0,
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qdev_get_gpio_in(gicdev,
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intidbase + VIRTUAL_PMU_IRQ));
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sysbus_connect_irq(gicsbd, i,
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qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
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sysbus_connect_irq(gicsbd, i + machine->smp.cpus,
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qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
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sysbus_connect_irq(gicsbd, i + 2 * machine->smp.cpus,
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qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
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sysbus_connect_irq(gicsbd, i + 3 * machine->smp.cpus,
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qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
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}
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}
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/*
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* Create UART uartno, and map it into the MemoryRegion mem at address baseaddr.
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* The qemu_irq arguments are where we connect the various IRQs from the UART.
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*/
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static void create_uart(MPS3RMachineState *mms, int uartno, MemoryRegion *mem,
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hwaddr baseaddr, qemu_irq txirq, qemu_irq rxirq,
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qemu_irq txoverirq, qemu_irq rxoverirq,
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qemu_irq combirq)
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{
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g_autofree char *s = g_strdup_printf("uart%d", uartno);
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SysBusDevice *sbd;
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assert(uartno < ARRAY_SIZE(mms->uart));
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object_initialize_child(OBJECT(mms), s, &mms->uart[uartno],
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TYPE_CMSDK_APB_UART);
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qdev_prop_set_uint32(DEVICE(&mms->uart[uartno]), "pclk-frq", CLK_FRQ);
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qdev_prop_set_chr(DEVICE(&mms->uart[uartno]), "chardev", serial_hd(uartno));
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sbd = SYS_BUS_DEVICE(&mms->uart[uartno]);
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sysbus_realize(sbd, &error_fatal);
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memory_region_add_subregion(mem, baseaddr,
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sysbus_mmio_get_region(sbd, 0));
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sysbus_connect_irq(sbd, 0, txirq);
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sysbus_connect_irq(sbd, 1, rxirq);
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sysbus_connect_irq(sbd, 2, txoverirq);
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sysbus_connect_irq(sbd, 3, rxoverirq);
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sysbus_connect_irq(sbd, 4, combirq);
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}
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static void mps3r_common_init(MachineState *machine)
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{
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MPS3RMachineState *mms = MPS3R_MACHINE(machine);
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MPS3RMachineClass *mmc = MPS3R_MACHINE_GET_CLASS(mms);
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MemoryRegion *sysmem = get_system_memory();
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DeviceState *gicdev;
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QList *oscclk;
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mms->clk = clock_new(OBJECT(machine), "CLK");
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clock_set_hz(mms->clk, CLK_FRQ);
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for (const RAMInfo *ri = mmc->raminfo; ri->name; ri++) {
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MemoryRegion *mr = mr_for_raminfo(mms, ri);
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memory_region_add_subregion(sysmem, ri->base, mr);
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}
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assert(machine->smp.cpus <= MPS3R_CPU_MAX);
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for (int i = 0; i < machine->smp.cpus; i++) {
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g_autofree char *sysmem_name = g_strdup_printf("cpu-%d-memory", i);
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g_autofree char *ramname = g_strdup_printf("cpu-%d-memory", i);
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g_autofree char *alias_name = g_strdup_printf("sysmem-alias-%d", i);
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/*
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* Each CPU has some private RAM/peripherals, so create the container
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* which will house those, with the whole-machine system memory being
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* used where there's no CPU-specific device. Note that we need the
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* sysmem_alias aliases because we can't put one MR (the original
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* 'sysmem') into more than one other MR.
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*/
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memory_region_init(&mms->cpu_sysmem[i], OBJECT(machine),
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sysmem_name, UINT64_MAX);
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memory_region_init_alias(&mms->sysmem_alias[i], OBJECT(machine),
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alias_name, sysmem, 0, UINT64_MAX);
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memory_region_add_subregion_overlap(&mms->cpu_sysmem[i], 0,
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&mms->sysmem_alias[i], -1);
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mms->cpu[i] = object_new(machine->cpu_type);
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object_property_set_link(mms->cpu[i], "memory",
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OBJECT(&mms->cpu_sysmem[i]), &error_abort);
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object_property_set_int(mms->cpu[i], "reset-cbar",
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PERIPHBASE, &error_abort);
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qdev_realize(DEVICE(mms->cpu[i]), NULL, &error_fatal);
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object_unref(mms->cpu[i]);
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/* Per-CPU RAM */
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memory_region_init_ram(&mms->cpu_ram[i], NULL, ramname,
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0x1000, &error_fatal);
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memory_region_add_subregion(&mms->cpu_sysmem[i], 0xe7c01000,
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&mms->cpu_ram[i]);
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}
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create_gic(mms, sysmem);
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gicdev = DEVICE(&mms->gic);
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/*
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* UARTs 0 and 1 are per-CPU; their interrupts are wired to
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* the relevant CPU's PPI 0..3, aka INTID 16..19
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*/
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for (int i = 0; i < machine->smp.cpus; i++) {
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int intidbase = NUM_SPIS + i * GIC_INTERNAL;
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g_autofree char *s = g_strdup_printf("cpu-uart-oflow-orgate%d", i);
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DeviceState *orgate;
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/* The two overflow IRQs from the UART are ORed together into PPI 3 */
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object_initialize_child(OBJECT(mms), s, &mms->cpu_uart_oflow[i],
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TYPE_OR_IRQ);
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orgate = DEVICE(&mms->cpu_uart_oflow[i]);
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qdev_prop_set_uint32(orgate, "num-lines", 2);
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qdev_realize(orgate, NULL, &error_fatal);
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qdev_connect_gpio_out(orgate, 0,
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qdev_get_gpio_in(gicdev, intidbase + 19));
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create_uart(mms, i, &mms->cpu_sysmem[i], 0xe7c00000,
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qdev_get_gpio_in(gicdev, intidbase + 17), /* tx */
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qdev_get_gpio_in(gicdev, intidbase + 16), /* rx */
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qdev_get_gpio_in(orgate, 0), /* txover */
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qdev_get_gpio_in(orgate, 1), /* rxover */
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qdev_get_gpio_in(gicdev, intidbase + 18) /* combined */);
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}
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/*
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* UARTs 2 to 5 are whole-system; all overflow IRQs are ORed
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* together into IRQ 17
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*/
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object_initialize_child(OBJECT(mms), "uart-oflow-orgate",
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&mms->uart_oflow, TYPE_OR_IRQ);
|
|
qdev_prop_set_uint32(DEVICE(&mms->uart_oflow), "num-lines",
|
|
MPS3R_UART_MAX * 2);
|
|
qdev_realize(DEVICE(&mms->uart_oflow), NULL, &error_fatal);
|
|
qdev_connect_gpio_out(DEVICE(&mms->uart_oflow), 0,
|
|
qdev_get_gpio_in(gicdev, 17));
|
|
|
|
for (int i = 0; i < MPS3R_UART_MAX; i++) {
|
|
hwaddr baseaddr = 0xe0205000 + i * 0x1000;
|
|
int rxirq = 5 + i * 2, txirq = 6 + i * 2, combirq = 13 + i;
|
|
|
|
create_uart(mms, i + MPS3R_CPU_MAX, sysmem, baseaddr,
|
|
qdev_get_gpio_in(gicdev, txirq),
|
|
qdev_get_gpio_in(gicdev, rxirq),
|
|
qdev_get_gpio_in(DEVICE(&mms->uart_oflow), i * 2),
|
|
qdev_get_gpio_in(DEVICE(&mms->uart_oflow), i * 2 + 1),
|
|
qdev_get_gpio_in(gicdev, combirq));
|
|
}
|
|
|
|
for (int i = 0; i < 4; i++) {
|
|
/* CMSDK GPIO controllers */
|
|
g_autofree char *s = g_strdup_printf("gpio%d", i);
|
|
create_unimplemented_device(s, 0xe0000000 + i * 0x1000, 0x1000);
|
|
}
|
|
|
|
object_initialize_child(OBJECT(mms), "watchdog", &mms->watchdog,
|
|
TYPE_CMSDK_APB_WATCHDOG);
|
|
qdev_connect_clock_in(DEVICE(&mms->watchdog), "WDOGCLK", mms->clk);
|
|
sysbus_realize(SYS_BUS_DEVICE(&mms->watchdog), &error_fatal);
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&mms->watchdog), 0,
|
|
qdev_get_gpio_in(gicdev, 0));
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(&mms->watchdog), 0, 0xe0100000);
|
|
|
|
object_initialize_child(OBJECT(mms), "dualtimer", &mms->dualtimer,
|
|
TYPE_CMSDK_APB_DUALTIMER);
|
|
qdev_connect_clock_in(DEVICE(&mms->dualtimer), "TIMCLK", mms->clk);
|
|
sysbus_realize(SYS_BUS_DEVICE(&mms->dualtimer), &error_fatal);
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 0,
|
|
qdev_get_gpio_in(gicdev, 3));
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 1,
|
|
qdev_get_gpio_in(gicdev, 1));
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 2,
|
|
qdev_get_gpio_in(gicdev, 2));
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(&mms->dualtimer), 0, 0xe0101000);
|
|
|
|
for (int i = 0; i < ARRAY_SIZE(mms->i2c); i++) {
|
|
static const hwaddr i2cbase[] = {0xe0102000, /* Touch */
|
|
0xe0103000, /* Audio */
|
|
0xe0107000, /* Shield0 */
|
|
0xe0108000, /* Shield1 */
|
|
0xe0109000}; /* DDR4 EEPROM */
|
|
g_autofree char *s = g_strdup_printf("i2c%d", i);
|
|
|
|
object_initialize_child(OBJECT(mms), s, &mms->i2c[i],
|
|
TYPE_ARM_SBCON_I2C);
|
|
sysbus_realize(SYS_BUS_DEVICE(&mms->i2c[i]), &error_fatal);
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(&mms->i2c[i]), 0, i2cbase[i]);
|
|
if (i != 2 && i != 3) {
|
|
/*
|
|
* internal-only bus: mark it full to avoid user-created
|
|
* i2c devices being plugged into it.
|
|
*/
|
|
qbus_mark_full(qdev_get_child_bus(DEVICE(&mms->i2c[i]), "i2c"));
|
|
}
|
|
}
|
|
|
|
for (int i = 0; i < ARRAY_SIZE(mms->spi); i++) {
|
|
g_autofree char *s = g_strdup_printf("spi%d", i);
|
|
hwaddr baseaddr = 0xe0104000 + i * 0x1000;
|
|
|
|
object_initialize_child(OBJECT(mms), s, &mms->spi[i], TYPE_PL022);
|
|
sysbus_realize(SYS_BUS_DEVICE(&mms->spi[i]), &error_fatal);
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(&mms->spi[i]), 0, baseaddr);
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&mms->spi[i]), 0,
|
|
qdev_get_gpio_in(gicdev, 22 + i));
|
|
}
|
|
|
|
object_initialize_child(OBJECT(mms), "scc", &mms->scc, TYPE_MPS2_SCC);
|
|
qdev_prop_set_uint32(DEVICE(&mms->scc), "scc-cfg0", 0);
|
|
qdev_prop_set_uint32(DEVICE(&mms->scc), "scc-cfg4", 0x2);
|
|
qdev_prop_set_uint32(DEVICE(&mms->scc), "scc-aid", 0x00200008);
|
|
qdev_prop_set_uint32(DEVICE(&mms->scc), "scc-id", 0x41055360);
|
|
oscclk = qlist_new();
|
|
for (int i = 0; i < ARRAY_SIZE(an536_oscclk); i++) {
|
|
qlist_append_int(oscclk, an536_oscclk[i]);
|
|
}
|
|
qdev_prop_set_array(DEVICE(&mms->scc), "oscclk", oscclk);
|
|
sysbus_realize(SYS_BUS_DEVICE(&mms->scc), &error_fatal);
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(&mms->scc), 0, 0xe0200000);
|
|
|
|
create_unimplemented_device("i2s-audio", 0xe0201000, 0x1000);
|
|
|
|
object_initialize_child(OBJECT(mms), "fpgaio", &mms->fpgaio,
|
|
TYPE_MPS2_FPGAIO);
|
|
qdev_prop_set_uint32(DEVICE(&mms->fpgaio), "prescale-clk", an536_oscclk[1]);
|
|
qdev_prop_set_uint32(DEVICE(&mms->fpgaio), "num-leds", 10);
|
|
qdev_prop_set_bit(DEVICE(&mms->fpgaio), "has-switches", true);
|
|
qdev_prop_set_bit(DEVICE(&mms->fpgaio), "has-dbgctrl", false);
|
|
sysbus_realize(SYS_BUS_DEVICE(&mms->fpgaio), &error_fatal);
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(&mms->fpgaio), 0, 0xe0202000);
|
|
|
|
create_unimplemented_device("clcd", 0xe0209000, 0x1000);
|
|
|
|
object_initialize_child(OBJECT(mms), "rtc", &mms->rtc, TYPE_PL031);
|
|
sysbus_realize(SYS_BUS_DEVICE(&mms->rtc), &error_fatal);
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(&mms->rtc), 0, 0xe020a000);
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&mms->rtc), 0,
|
|
qdev_get_gpio_in(gicdev, 4));
|
|
|
|
/*
|
|
* In hardware this is a LAN9220; the LAN9118 is software compatible
|
|
* except that it doesn't support the checksum-offload feature.
|
|
*/
|
|
lan9118_init(0xe0300000,
|
|
qdev_get_gpio_in(gicdev, 18));
|
|
|
|
create_unimplemented_device("usb", 0xe0301000, 0x1000);
|
|
create_unimplemented_device("qspi-write-config", 0xe0600000, 0x1000);
|
|
|
|
mms->bootinfo.ram_size = machine->ram_size;
|
|
mms->bootinfo.board_id = -1;
|
|
mms->bootinfo.loader_start = mmc->loader_start;
|
|
mms->bootinfo.write_secondary_boot = mps3r_write_secondary_boot;
|
|
mms->bootinfo.secondary_cpu_reset_hook = mps3r_secondary_cpu_reset;
|
|
arm_load_kernel(ARM_CPU(mms->cpu[0]), machine, &mms->bootinfo);
|
|
}
|
|
|
|
static void mps3r_set_default_ram_info(MPS3RMachineClass *mmc)
|
|
{
|
|
/*
|
|
* Set mc->default_ram_size and default_ram_id from the
|
|
* information in mmc->raminfo.
|
|
*/
|
|
MachineClass *mc = MACHINE_CLASS(mmc);
|
|
const RAMInfo *p;
|
|
|
|
for (p = mmc->raminfo; p->name; p++) {
|
|
if (p->mrindex < 0) {
|
|
/* Found the entry for "system memory" */
|
|
mc->default_ram_size = p->size;
|
|
mc->default_ram_id = p->name;
|
|
mmc->loader_start = p->base;
|
|
return;
|
|
}
|
|
}
|
|
g_assert_not_reached();
|
|
}
|
|
|
|
static void mps3r_class_init(ObjectClass *oc, void *data)
|
|
{
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
|
|
mc->init = mps3r_common_init;
|
|
}
|
|
|
|
static void mps3r_an536_class_init(ObjectClass *oc, void *data)
|
|
{
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
MPS3RMachineClass *mmc = MPS3R_MACHINE_CLASS(oc);
|
|
static const char * const valid_cpu_types[] = {
|
|
ARM_CPU_TYPE_NAME("cortex-r52"),
|
|
NULL
|
|
};
|
|
|
|
mc->desc = "ARM MPS3 with AN536 FPGA image for Cortex-R52";
|
|
/*
|
|
* In the real FPGA image there are always two cores, but the standard
|
|
* initial setting for the SCC SYSCON 0x000 register is 0x21, meaning
|
|
* that the second core is held in reset and halted. Many images built for
|
|
* the board do not expect the second core to run at startup (especially
|
|
* since on the real FPGA image it is not possible to use LDREX/STREX
|
|
* in RAM between the two cores, so a true SMP setup isn't supported).
|
|
*
|
|
* As QEMU's equivalent of this, we support both -smp 1 and -smp 2,
|
|
* with the default being -smp 1. This seems a more intuitive UI for
|
|
* QEMU users than, for instance, having a machine property to allow
|
|
* the user to set the initial value of the SYSCON 0x000 register.
|
|
*/
|
|
mc->default_cpus = 1;
|
|
mc->min_cpus = 1;
|
|
mc->max_cpus = 2;
|
|
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-r52");
|
|
mc->valid_cpu_types = valid_cpu_types;
|
|
mmc->raminfo = an536_raminfo;
|
|
mps3r_set_default_ram_info(mmc);
|
|
}
|
|
|
|
static const TypeInfo mps3r_machine_types[] = {
|
|
{
|
|
.name = TYPE_MPS3R_MACHINE,
|
|
.parent = TYPE_MACHINE,
|
|
.abstract = true,
|
|
.instance_size = sizeof(MPS3RMachineState),
|
|
.class_size = sizeof(MPS3RMachineClass),
|
|
.class_init = mps3r_class_init,
|
|
}, {
|
|
.name = TYPE_MPS3R_AN536_MACHINE,
|
|
.parent = TYPE_MPS3R_MACHINE,
|
|
.class_init = mps3r_an536_class_init,
|
|
},
|
|
};
|
|
|
|
DEFINE_TYPES(mps3r_machine_types);
|