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734 lines
26 KiB
C
734 lines
26 KiB
C
/*
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* ASPEED SoC 27x0 family
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*
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* Copyright (C) 2024 ASPEED Technology Inc.
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*
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* This code is licensed under the GPL version 2 or later. See
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* the COPYING file in the top-level directory.
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*
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* Implementation extracted from the AST2600 and adapted for AST27x0.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "hw/misc/unimp.h"
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#include "hw/arm/aspeed_soc.h"
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#include "hw/arm/bsa.h"
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#include "qemu/module.h"
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#include "qemu/error-report.h"
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#include "hw/i2c/aspeed_i2c.h"
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#include "net/net.h"
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#include "sysemu/sysemu.h"
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#include "hw/intc/arm_gicv3.h"
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#include "qapi/qmp/qlist.h"
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#include "qemu/log.h"
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static const hwaddr aspeed_soc_ast2700_memmap[] = {
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[ASPEED_DEV_SPI_BOOT] = 0x400000000,
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[ASPEED_DEV_SRAM] = 0x10000000,
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[ASPEED_DEV_SDMC] = 0x12C00000,
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[ASPEED_DEV_SCU] = 0x12C02000,
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[ASPEED_DEV_SCUIO] = 0x14C02000,
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[ASPEED_DEV_UART0] = 0X14C33000,
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[ASPEED_DEV_UART1] = 0X14C33100,
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[ASPEED_DEV_UART2] = 0X14C33200,
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[ASPEED_DEV_UART3] = 0X14C33300,
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[ASPEED_DEV_UART4] = 0X12C1A000,
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[ASPEED_DEV_UART5] = 0X14C33400,
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[ASPEED_DEV_UART6] = 0X14C33500,
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[ASPEED_DEV_UART7] = 0X14C33600,
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[ASPEED_DEV_UART8] = 0X14C33700,
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[ASPEED_DEV_UART9] = 0X14C33800,
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[ASPEED_DEV_UART10] = 0X14C33900,
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[ASPEED_DEV_UART11] = 0X14C33A00,
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[ASPEED_DEV_UART12] = 0X14C33B00,
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[ASPEED_DEV_WDT] = 0x14C37000,
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[ASPEED_DEV_VUART] = 0X14C30000,
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[ASPEED_DEV_FMC] = 0x14000000,
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[ASPEED_DEV_SPI0] = 0x14010000,
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[ASPEED_DEV_SPI1] = 0x14020000,
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[ASPEED_DEV_SPI2] = 0x14030000,
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[ASPEED_DEV_SDRAM] = 0x400000000,
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[ASPEED_DEV_MII1] = 0x14040000,
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[ASPEED_DEV_MII2] = 0x14040008,
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[ASPEED_DEV_MII3] = 0x14040010,
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[ASPEED_DEV_ETH1] = 0x14050000,
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[ASPEED_DEV_ETH2] = 0x14060000,
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[ASPEED_DEV_ETH3] = 0x14070000,
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[ASPEED_DEV_EMMC] = 0x12090000,
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[ASPEED_DEV_INTC] = 0x12100000,
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[ASPEED_DEV_SLI] = 0x12C17000,
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[ASPEED_DEV_SLIIO] = 0x14C1E000,
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[ASPEED_GIC_DIST] = 0x12200000,
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[ASPEED_GIC_REDIST] = 0x12280000,
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[ASPEED_DEV_ADC] = 0x14C00000,
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[ASPEED_DEV_I2C] = 0x14C0F000,
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[ASPEED_DEV_GPIO] = 0x14C0B000,
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[ASPEED_DEV_RTC] = 0x12C0F000,
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};
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#define AST2700_MAX_IRQ 256
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/* Shared Peripheral Interrupt values below are offset by -32 from datasheet */
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static const int aspeed_soc_ast2700_irqmap[] = {
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[ASPEED_DEV_UART0] = 132,
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[ASPEED_DEV_UART1] = 132,
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[ASPEED_DEV_UART2] = 132,
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[ASPEED_DEV_UART3] = 132,
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[ASPEED_DEV_UART4] = 8,
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[ASPEED_DEV_UART5] = 132,
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[ASPEED_DEV_UART6] = 132,
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[ASPEED_DEV_UART7] = 132,
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[ASPEED_DEV_UART8] = 132,
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[ASPEED_DEV_UART9] = 132,
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[ASPEED_DEV_UART10] = 132,
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[ASPEED_DEV_UART11] = 132,
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[ASPEED_DEV_UART12] = 132,
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[ASPEED_DEV_FMC] = 131,
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[ASPEED_DEV_SDMC] = 0,
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[ASPEED_DEV_SCU] = 12,
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[ASPEED_DEV_ADC] = 130,
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[ASPEED_DEV_XDMA] = 5,
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[ASPEED_DEV_EMMC] = 15,
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[ASPEED_DEV_GPIO] = 130,
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[ASPEED_DEV_RTC] = 13,
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[ASPEED_DEV_TIMER1] = 16,
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[ASPEED_DEV_TIMER2] = 17,
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[ASPEED_DEV_TIMER3] = 18,
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[ASPEED_DEV_TIMER4] = 19,
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[ASPEED_DEV_TIMER5] = 20,
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[ASPEED_DEV_TIMER6] = 21,
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[ASPEED_DEV_TIMER7] = 22,
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[ASPEED_DEV_TIMER8] = 23,
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[ASPEED_DEV_WDT] = 131,
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[ASPEED_DEV_PWM] = 131,
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[ASPEED_DEV_LPC] = 128,
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[ASPEED_DEV_IBT] = 128,
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[ASPEED_DEV_I2C] = 130,
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[ASPEED_DEV_PECI] = 133,
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[ASPEED_DEV_ETH1] = 132,
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[ASPEED_DEV_ETH2] = 132,
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[ASPEED_DEV_ETH3] = 132,
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[ASPEED_DEV_HACE] = 4,
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[ASPEED_DEV_KCS] = 128,
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[ASPEED_DEV_DP] = 28,
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[ASPEED_DEV_I3C] = 131,
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};
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/* GICINT 128 */
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static const int aspeed_soc_ast2700_gic128_intcmap[] = {
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[ASPEED_DEV_LPC] = 0,
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[ASPEED_DEV_IBT] = 2,
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[ASPEED_DEV_KCS] = 4,
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};
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/* GICINT 130 */
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static const int aspeed_soc_ast2700_gic130_intcmap[] = {
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[ASPEED_DEV_I2C] = 0,
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[ASPEED_DEV_ADC] = 16,
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[ASPEED_DEV_GPIO] = 18,
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};
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/* GICINT 131 */
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static const int aspeed_soc_ast2700_gic131_intcmap[] = {
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[ASPEED_DEV_I3C] = 0,
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[ASPEED_DEV_WDT] = 16,
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[ASPEED_DEV_FMC] = 25,
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[ASPEED_DEV_PWM] = 29,
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};
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/* GICINT 132 */
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static const int aspeed_soc_ast2700_gic132_intcmap[] = {
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[ASPEED_DEV_ETH1] = 0,
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[ASPEED_DEV_ETH2] = 1,
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[ASPEED_DEV_ETH3] = 2,
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[ASPEED_DEV_UART0] = 7,
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[ASPEED_DEV_UART1] = 8,
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[ASPEED_DEV_UART2] = 9,
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[ASPEED_DEV_UART3] = 10,
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[ASPEED_DEV_UART5] = 11,
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[ASPEED_DEV_UART6] = 12,
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[ASPEED_DEV_UART7] = 13,
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[ASPEED_DEV_UART8] = 14,
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[ASPEED_DEV_UART9] = 15,
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[ASPEED_DEV_UART10] = 16,
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[ASPEED_DEV_UART11] = 17,
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[ASPEED_DEV_UART12] = 18,
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};
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/* GICINT 133 */
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static const int aspeed_soc_ast2700_gic133_intcmap[] = {
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[ASPEED_DEV_PECI] = 4,
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};
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/* GICINT 128 ~ 136 */
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struct gic_intc_irq_info {
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int irq;
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const int *ptr;
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};
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static const struct gic_intc_irq_info aspeed_soc_ast2700_gic_intcmap[] = {
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{128, aspeed_soc_ast2700_gic128_intcmap},
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{129, NULL},
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{130, aspeed_soc_ast2700_gic130_intcmap},
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{131, aspeed_soc_ast2700_gic131_intcmap},
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{132, aspeed_soc_ast2700_gic132_intcmap},
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{133, aspeed_soc_ast2700_gic133_intcmap},
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{134, NULL},
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{135, NULL},
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{136, NULL},
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};
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static qemu_irq aspeed_soc_ast2700_get_irq(AspeedSoCState *s, int dev)
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{
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Aspeed27x0SoCState *a = ASPEED27X0_SOC(s);
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AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
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int i;
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for (i = 0; i < ARRAY_SIZE(aspeed_soc_ast2700_gic_intcmap); i++) {
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if (sc->irqmap[dev] == aspeed_soc_ast2700_gic_intcmap[i].irq) {
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assert(aspeed_soc_ast2700_gic_intcmap[i].ptr);
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return qdev_get_gpio_in(DEVICE(&a->intc.orgates[i]),
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aspeed_soc_ast2700_gic_intcmap[i].ptr[dev]);
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}
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}
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return qdev_get_gpio_in(DEVICE(&a->gic), sc->irqmap[dev]);
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}
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static qemu_irq aspeed_soc_ast2700_get_irq_index(AspeedSoCState *s, int dev,
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int index)
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{
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Aspeed27x0SoCState *a = ASPEED27X0_SOC(s);
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AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
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int i;
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for (i = 0; i < ARRAY_SIZE(aspeed_soc_ast2700_gic_intcmap); i++) {
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if (sc->irqmap[dev] == aspeed_soc_ast2700_gic_intcmap[i].irq) {
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assert(aspeed_soc_ast2700_gic_intcmap[i].ptr);
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return qdev_get_gpio_in(DEVICE(&a->intc.orgates[i]),
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aspeed_soc_ast2700_gic_intcmap[i].ptr[dev] + index);
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}
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}
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/*
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* Invalid orgate index, device irq should be 128 to 136.
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*/
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g_assert_not_reached();
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}
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static uint64_t aspeed_ram_capacity_read(void *opaque, hwaddr addr,
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unsigned int size)
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{
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: DRAM read out of ram size, addr:0x%" PRIx64 "\n",
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__func__, addr);
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return 0;
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}
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static void aspeed_ram_capacity_write(void *opaque, hwaddr addr, uint64_t data,
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unsigned int size)
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{
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AspeedSoCState *s = ASPEED_SOC(opaque);
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ram_addr_t ram_size;
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MemTxResult result;
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ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size",
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&error_abort);
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assert(ram_size > 0);
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/*
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* Emulate ddr capacity hardware behavior.
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* If writes the data to the address which is beyond the ram size,
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* it would write the data to the "address % ram_size".
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*/
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result = address_space_write(&s->dram_as, addr % ram_size,
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MEMTXATTRS_UNSPECIFIED, &data, 4);
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if (result != MEMTX_OK) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: DRAM write failed, addr:0x%" HWADDR_PRIx
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", data :0x%" PRIx64 "\n",
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__func__, addr % ram_size, data);
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}
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}
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static const MemoryRegionOps aspeed_ram_capacity_ops = {
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.read = aspeed_ram_capacity_read,
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.write = aspeed_ram_capacity_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid = {
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.min_access_size = 1,
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.max_access_size = 8,
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},
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};
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/*
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* SDMC should be realized first to get correct RAM size and max size
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* values
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*/
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static bool aspeed_soc_ast2700_dram_init(DeviceState *dev, Error **errp)
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{
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ram_addr_t ram_size, max_ram_size;
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Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev);
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AspeedSoCState *s = ASPEED_SOC(dev);
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AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
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ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size",
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&error_abort);
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max_ram_size = object_property_get_uint(OBJECT(&s->sdmc), "max-ram-size",
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&error_abort);
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memory_region_init(&s->dram_container, OBJECT(s), "ram-container",
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ram_size);
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memory_region_add_subregion(&s->dram_container, 0, s->dram_mr);
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address_space_init(&s->dram_as, s->dram_mr, "dram");
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/*
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* Add a memory region beyond the RAM region to emulate
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* ddr capacity hardware behavior.
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*/
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if (ram_size < max_ram_size) {
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memory_region_init_io(&a->dram_empty, OBJECT(s),
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&aspeed_ram_capacity_ops, s,
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"ram-empty", max_ram_size - ram_size);
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memory_region_add_subregion(s->memory,
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sc->memmap[ASPEED_DEV_SDRAM] + ram_size,
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&a->dram_empty);
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}
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memory_region_add_subregion(s->memory,
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sc->memmap[ASPEED_DEV_SDRAM], &s->dram_container);
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return true;
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}
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static void aspeed_soc_ast2700_init(Object *obj)
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{
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Aspeed27x0SoCState *a = ASPEED27X0_SOC(obj);
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AspeedSoCState *s = ASPEED_SOC(obj);
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AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
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int i;
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char socname[8];
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char typename[64];
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if (sscanf(sc->name, "%7s", socname) != 1) {
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g_assert_not_reached();
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}
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for (i = 0; i < sc->num_cpus; i++) {
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object_initialize_child(obj, "cpu[*]", &a->cpu[i],
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aspeed_soc_cpu_type(sc));
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}
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object_initialize_child(obj, "gic", &a->gic, gicv3_class_name());
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object_initialize_child(obj, "scu", &s->scu, TYPE_ASPEED_2700_SCU);
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qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",
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sc->silicon_rev);
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object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu),
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"hw-strap1");
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object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu),
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"hw-strap2");
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object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),
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"hw-prot-key");
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object_initialize_child(obj, "scuio", &s->scuio, TYPE_ASPEED_2700_SCUIO);
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qdev_prop_set_uint32(DEVICE(&s->scuio), "silicon-rev",
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sc->silicon_rev);
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snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname);
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object_initialize_child(obj, "fmc", &s->fmc, typename);
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for (i = 0; i < sc->spis_num; i++) {
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snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i, socname);
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object_initialize_child(obj, "spi[*]", &s->spi[i], typename);
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}
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snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname);
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object_initialize_child(obj, "sdmc", &s->sdmc, typename);
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object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
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"ram-size");
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for (i = 0; i < sc->wdts_num; i++) {
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snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname);
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object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename);
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}
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for (i = 0; i < sc->macs_num; i++) {
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object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i],
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TYPE_FTGMAC100);
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object_initialize_child(obj, "mii[*]", &s->mii[i], TYPE_ASPEED_MII);
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}
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for (i = 0; i < sc->uarts_num; i++) {
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object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM);
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}
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object_initialize_child(obj, "sli", &s->sli, TYPE_ASPEED_2700_SLI);
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object_initialize_child(obj, "sliio", &s->sliio, TYPE_ASPEED_2700_SLIIO);
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object_initialize_child(obj, "intc", &a->intc, TYPE_ASPEED_2700_INTC);
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snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname);
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object_initialize_child(obj, "adc", &s->adc, typename);
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snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname);
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object_initialize_child(obj, "i2c", &s->i2c, typename);
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snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname);
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object_initialize_child(obj, "gpio", &s->gpio, typename);
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object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC);
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}
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/*
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* ASPEED ast2700 has 0x0 as cluster ID
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*
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* https://developer.arm.com/documentation/100236/0100/register-descriptions/aarch64-system-registers/multiprocessor-affinity-register--el1
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*/
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static uint64_t aspeed_calc_affinity(int cpu)
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{
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return (0x0 << ARM_AFF1_SHIFT) | cpu;
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}
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static bool aspeed_soc_ast2700_gic_realize(DeviceState *dev, Error **errp)
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{
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Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev);
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AspeedSoCState *s = ASPEED_SOC(dev);
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AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
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SysBusDevice *gicbusdev;
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DeviceState *gicdev;
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QList *redist_region_count;
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int i;
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gicbusdev = SYS_BUS_DEVICE(&a->gic);
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gicdev = DEVICE(&a->gic);
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qdev_prop_set_uint32(gicdev, "revision", 3);
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qdev_prop_set_uint32(gicdev, "num-cpu", sc->num_cpus);
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qdev_prop_set_uint32(gicdev, "num-irq", AST2700_MAX_IRQ + GIC_INTERNAL);
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|
|
redist_region_count = qlist_new();
|
|
qlist_append_int(redist_region_count, sc->num_cpus);
|
|
qdev_prop_set_array(gicdev, "redist-region-count", redist_region_count);
|
|
|
|
if (!sysbus_realize(gicbusdev, errp)) {
|
|
return false;
|
|
}
|
|
sysbus_mmio_map(gicbusdev, 0, sc->memmap[ASPEED_GIC_DIST]);
|
|
sysbus_mmio_map(gicbusdev, 1, sc->memmap[ASPEED_GIC_REDIST]);
|
|
|
|
for (i = 0; i < sc->num_cpus; i++) {
|
|
DeviceState *cpudev = DEVICE(&a->cpu[i]);
|
|
int intidbase = AST2700_MAX_IRQ + i * GIC_INTERNAL;
|
|
|
|
const int timer_irq[] = {
|
|
[GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ,
|
|
[GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,
|
|
[GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ,
|
|
[GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ,
|
|
};
|
|
int j;
|
|
|
|
for (j = 0; j < ARRAY_SIZE(timer_irq); j++) {
|
|
qdev_connect_gpio_out(cpudev, j,
|
|
qdev_get_gpio_in(gicdev, intidbase + timer_irq[j]));
|
|
}
|
|
|
|
qemu_irq irq = qdev_get_gpio_in(gicdev,
|
|
intidbase + ARCH_GIC_MAINT_IRQ);
|
|
qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt",
|
|
0, irq);
|
|
qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0,
|
|
qdev_get_gpio_in(gicdev, intidbase + VIRTUAL_PMU_IRQ));
|
|
|
|
sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
|
|
sysbus_connect_irq(gicbusdev, i + sc->num_cpus,
|
|
qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
|
|
sysbus_connect_irq(gicbusdev, i + 2 * sc->num_cpus,
|
|
qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
|
|
sysbus_connect_irq(gicbusdev, i + 3 * sc->num_cpus,
|
|
qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
|
|
{
|
|
int i;
|
|
Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev);
|
|
AspeedSoCState *s = ASPEED_SOC(dev);
|
|
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
|
|
AspeedINTCClass *ic = ASPEED_INTC_GET_CLASS(&a->intc);
|
|
g_autofree char *sram_name = NULL;
|
|
qemu_irq irq;
|
|
|
|
/* Default boot region (SPI memory or ROMs) */
|
|
memory_region_init(&s->spi_boot_container, OBJECT(s),
|
|
"aspeed.spi_boot_container", 0x400000000);
|
|
memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SPI_BOOT],
|
|
&s->spi_boot_container);
|
|
|
|
/* CPU */
|
|
for (i = 0; i < sc->num_cpus; i++) {
|
|
object_property_set_int(OBJECT(&a->cpu[i]), "mp-affinity",
|
|
aspeed_calc_affinity(i), &error_abort);
|
|
|
|
object_property_set_int(OBJECT(&a->cpu[i]), "cntfrq", 1125000000,
|
|
&error_abort);
|
|
object_property_set_link(OBJECT(&a->cpu[i]), "memory",
|
|
OBJECT(s->memory), &error_abort);
|
|
|
|
if (!qdev_realize(DEVICE(&a->cpu[i]), NULL, errp)) {
|
|
return;
|
|
}
|
|
}
|
|
|
|
/* GIC */
|
|
if (!aspeed_soc_ast2700_gic_realize(dev, errp)) {
|
|
return;
|
|
}
|
|
|
|
/* INTC */
|
|
if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc), errp)) {
|
|
return;
|
|
}
|
|
|
|
aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc), 0,
|
|
sc->memmap[ASPEED_DEV_INTC]);
|
|
|
|
/* GICINT orgates -> INTC -> GIC */
|
|
for (i = 0; i < ic->num_ints; i++) {
|
|
qdev_connect_gpio_out(DEVICE(&a->intc.orgates[i]), 0,
|
|
qdev_get_gpio_in(DEVICE(&a->intc), i));
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc), i,
|
|
qdev_get_gpio_in(DEVICE(&a->gic),
|
|
aspeed_soc_ast2700_gic_intcmap[i].irq));
|
|
}
|
|
|
|
/* SRAM */
|
|
sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index);
|
|
if (!memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size,
|
|
errp)) {
|
|
return;
|
|
}
|
|
memory_region_add_subregion(s->memory,
|
|
sc->memmap[ASPEED_DEV_SRAM], &s->sram);
|
|
|
|
/* SCU */
|
|
if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
|
|
return;
|
|
}
|
|
aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]);
|
|
|
|
/* SCU1 */
|
|
if (!sysbus_realize(SYS_BUS_DEVICE(&s->scuio), errp)) {
|
|
return;
|
|
}
|
|
aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scuio), 0,
|
|
sc->memmap[ASPEED_DEV_SCUIO]);
|
|
|
|
/* UART */
|
|
if (!aspeed_soc_uart_realize(s, errp)) {
|
|
return;
|
|
}
|
|
|
|
/* FMC, The number of CS is set at the board level */
|
|
object_property_set_int(OBJECT(&s->fmc), "dram-base",
|
|
sc->memmap[ASPEED_DEV_SDRAM],
|
|
&error_abort);
|
|
object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr),
|
|
&error_abort);
|
|
if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) {
|
|
return;
|
|
}
|
|
aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]);
|
|
aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 1,
|
|
ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base);
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
|
|
aspeed_soc_get_irq(s, ASPEED_DEV_FMC));
|
|
|
|
/* Set up an alias on the FMC CE0 region (boot default) */
|
|
MemoryRegion *fmc0_mmio = &s->fmc.flashes[0].mmio;
|
|
memory_region_init_alias(&s->spi_boot, OBJECT(s), "aspeed.spi_boot",
|
|
fmc0_mmio, 0, memory_region_size(fmc0_mmio));
|
|
memory_region_add_subregion(&s->spi_boot_container, 0x0, &s->spi_boot);
|
|
|
|
/* SPI */
|
|
for (i = 0; i < sc->spis_num; i++) {
|
|
object_property_set_link(OBJECT(&s->spi[i]), "dram",
|
|
OBJECT(s->dram_mr), &error_abort);
|
|
if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
|
|
return;
|
|
}
|
|
aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 0,
|
|
sc->memmap[ASPEED_DEV_SPI0 + i]);
|
|
aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 1,
|
|
ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base);
|
|
}
|
|
|
|
/*
|
|
* SDMC - SDRAM Memory Controller
|
|
* The SDMC controller is unlocked at SPL stage.
|
|
* At present, only supports to emulate booting
|
|
* start from u-boot stage. Set SDMC controller
|
|
* unlocked by default. It is a temporarily solution.
|
|
*/
|
|
object_property_set_bool(OBJECT(&s->sdmc), "unlocked", true,
|
|
&error_abort);
|
|
if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) {
|
|
return;
|
|
}
|
|
aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdmc), 0,
|
|
sc->memmap[ASPEED_DEV_SDMC]);
|
|
|
|
/* RAM */
|
|
if (!aspeed_soc_ast2700_dram_init(dev, errp)) {
|
|
return;
|
|
}
|
|
|
|
/* Net */
|
|
for (i = 0; i < sc->macs_num; i++) {
|
|
object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true,
|
|
&error_abort);
|
|
object_property_set_bool(OBJECT(&s->ftgmac100[i]), "dma64", true,
|
|
&error_abort);
|
|
if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) {
|
|
return;
|
|
}
|
|
aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
|
|
sc->memmap[ASPEED_DEV_ETH1 + i]);
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
|
|
aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i));
|
|
|
|
object_property_set_link(OBJECT(&s->mii[i]), "nic",
|
|
OBJECT(&s->ftgmac100[i]), &error_abort);
|
|
if (!sysbus_realize(SYS_BUS_DEVICE(&s->mii[i]), errp)) {
|
|
return;
|
|
}
|
|
|
|
aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->mii[i]), 0,
|
|
sc->memmap[ASPEED_DEV_MII1 + i]);
|
|
}
|
|
|
|
/* Watch dog */
|
|
for (i = 0; i < sc->wdts_num; i++) {
|
|
AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
|
|
hwaddr wdt_offset = sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize;
|
|
|
|
object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu),
|
|
&error_abort);
|
|
if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) {
|
|
return;
|
|
}
|
|
aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset);
|
|
}
|
|
|
|
/* SLI */
|
|
if (!sysbus_realize(SYS_BUS_DEVICE(&s->sli), errp)) {
|
|
return;
|
|
}
|
|
aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sli), 0, sc->memmap[ASPEED_DEV_SLI]);
|
|
|
|
if (!sysbus_realize(SYS_BUS_DEVICE(&s->sliio), errp)) {
|
|
return;
|
|
}
|
|
aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sliio), 0,
|
|
sc->memmap[ASPEED_DEV_SLIIO]);
|
|
|
|
/* ADC */
|
|
if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) {
|
|
return;
|
|
}
|
|
aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]);
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0,
|
|
aspeed_soc_get_irq(s, ASPEED_DEV_ADC));
|
|
|
|
/* I2C */
|
|
object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr),
|
|
&error_abort);
|
|
if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) {
|
|
return;
|
|
}
|
|
aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]);
|
|
for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) {
|
|
/*
|
|
* The AST2700 I2C controller has one source INTC per bus.
|
|
* I2C buses interrupt are connected to GICINT130_INTC
|
|
* from bit 0 to bit 15.
|
|
* I2C bus 0 is connected to GICINT130_INTC at bit 0.
|
|
* I2C bus 15 is connected to GICINT130_INTC at bit 15.
|
|
*/
|
|
irq = aspeed_soc_ast2700_get_irq_index(s, ASPEED_DEV_I2C, i);
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq);
|
|
}
|
|
|
|
/* GPIO */
|
|
if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
|
|
return;
|
|
}
|
|
aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio), 0,
|
|
sc->memmap[ASPEED_DEV_GPIO]);
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0,
|
|
aspeed_soc_get_irq(s, ASPEED_DEV_GPIO));
|
|
|
|
/* RTC */
|
|
if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) {
|
|
return;
|
|
}
|
|
aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]);
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0,
|
|
aspeed_soc_get_irq(s, ASPEED_DEV_RTC));
|
|
|
|
create_unimplemented_device("ast2700.dpmcu", 0x11000000, 0x40000);
|
|
create_unimplemented_device("ast2700.iomem0", 0x12000000, 0x01000000);
|
|
create_unimplemented_device("ast2700.iomem1", 0x14000000, 0x01000000);
|
|
create_unimplemented_device("ast2700.ltpi", 0x30000000, 0x1000000);
|
|
create_unimplemented_device("ast2700.io", 0x0, 0x4000000);
|
|
}
|
|
|
|
static void aspeed_soc_ast2700_class_init(ObjectClass *oc, void *data)
|
|
{
|
|
static const char * const valid_cpu_types[] = {
|
|
ARM_CPU_TYPE_NAME("cortex-a35"),
|
|
NULL
|
|
};
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
|
AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
|
|
|
|
/* Reason: The Aspeed SoC can only be instantiated from a board */
|
|
dc->user_creatable = false;
|
|
dc->realize = aspeed_soc_ast2700_realize;
|
|
|
|
sc->name = "ast2700-a0";
|
|
sc->valid_cpu_types = valid_cpu_types;
|
|
sc->silicon_rev = AST2700_A0_SILICON_REV;
|
|
sc->sram_size = 0x20000;
|
|
sc->spis_num = 3;
|
|
sc->wdts_num = 8;
|
|
sc->macs_num = 1;
|
|
sc->uarts_num = 13;
|
|
sc->num_cpus = 4;
|
|
sc->uarts_base = ASPEED_DEV_UART0;
|
|
sc->irqmap = aspeed_soc_ast2700_irqmap;
|
|
sc->memmap = aspeed_soc_ast2700_memmap;
|
|
sc->get_irq = aspeed_soc_ast2700_get_irq;
|
|
}
|
|
|
|
static const TypeInfo aspeed_soc_ast27x0_types[] = {
|
|
{
|
|
.name = TYPE_ASPEED27X0_SOC,
|
|
.parent = TYPE_ASPEED_SOC,
|
|
.instance_size = sizeof(Aspeed27x0SoCState),
|
|
.abstract = true,
|
|
}, {
|
|
.name = "ast2700-a0",
|
|
.parent = TYPE_ASPEED27X0_SOC,
|
|
.instance_init = aspeed_soc_ast2700_init,
|
|
.class_init = aspeed_soc_ast2700_class_init,
|
|
},
|
|
};
|
|
|
|
DEFINE_TYPES(aspeed_soc_ast27x0_types)
|