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664 lines
23 KiB
C
664 lines
23 KiB
C
/*
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* ARMV7M System emulation.
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*
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* Copyright (c) 2006-2007 CodeSourcery.
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* Written by Paul Brook
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*
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* This code is licensed under the GPL.
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*/
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#include "qemu/osdep.h"
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#include "hw/arm/armv7m.h"
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#include "qapi/error.h"
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#include "hw/sysbus.h"
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#include "hw/arm/boot.h"
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#include "hw/loader.h"
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#include "hw/qdev-properties.h"
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#include "hw/qdev-clock.h"
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#include "elf.h"
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#include "sysemu/reset.h"
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#include "qemu/error-report.h"
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#include "qemu/module.h"
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#include "qemu/log.h"
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#include "target/arm/idau.h"
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#include "target/arm/cpu.h"
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#include "target/arm/cpu-features.h"
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#include "target/arm/cpu-qom.h"
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#include "migration/vmstate.h"
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/* Bitbanded IO. Each word corresponds to a single bit. */
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/* Get the byte address of the real memory for a bitband access. */
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static inline hwaddr bitband_addr(BitBandState *s, hwaddr offset)
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{
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return s->base | (offset & 0x1ffffff) >> 5;
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}
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static MemTxResult bitband_read(void *opaque, hwaddr offset,
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uint64_t *data, unsigned size, MemTxAttrs attrs)
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{
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BitBandState *s = opaque;
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uint8_t buf[4];
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MemTxResult res;
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int bitpos, bit;
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hwaddr addr;
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assert(size <= 4);
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/* Find address in underlying memory and round down to multiple of size */
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addr = bitband_addr(s, offset) & (-size);
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res = address_space_read(&s->source_as, addr, attrs, buf, size);
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if (res) {
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return res;
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}
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/* Bit position in the N bytes read... */
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bitpos = (offset >> 2) & ((size * 8) - 1);
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/* ...converted to byte in buffer and bit in byte */
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bit = (buf[bitpos >> 3] >> (bitpos & 7)) & 1;
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*data = bit;
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return MEMTX_OK;
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}
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static MemTxResult bitband_write(void *opaque, hwaddr offset, uint64_t value,
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unsigned size, MemTxAttrs attrs)
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{
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BitBandState *s = opaque;
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uint8_t buf[4];
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MemTxResult res;
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int bitpos, bit;
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hwaddr addr;
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assert(size <= 4);
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/* Find address in underlying memory and round down to multiple of size */
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addr = bitband_addr(s, offset) & (-size);
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res = address_space_read(&s->source_as, addr, attrs, buf, size);
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if (res) {
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return res;
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}
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/* Bit position in the N bytes read... */
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bitpos = (offset >> 2) & ((size * 8) - 1);
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/* ...converted to byte in buffer and bit in byte */
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bit = 1 << (bitpos & 7);
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if (value & 1) {
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buf[bitpos >> 3] |= bit;
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} else {
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buf[bitpos >> 3] &= ~bit;
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}
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return address_space_write(&s->source_as, addr, attrs, buf, size);
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}
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static const MemoryRegionOps bitband_ops = {
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.read_with_attrs = bitband_read,
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.write_with_attrs = bitband_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.impl.min_access_size = 1,
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.impl.max_access_size = 4,
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.valid.min_access_size = 1,
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.valid.max_access_size = 4,
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};
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static void bitband_init(Object *obj)
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{
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BitBandState *s = BITBAND(obj);
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SysBusDevice *dev = SYS_BUS_DEVICE(obj);
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memory_region_init_io(&s->iomem, obj, &bitband_ops, s,
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"bitband", 0x02000000);
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sysbus_init_mmio(dev, &s->iomem);
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}
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static void bitband_realize(DeviceState *dev, Error **errp)
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{
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BitBandState *s = BITBAND(dev);
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if (!s->source_memory) {
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error_setg(errp, "source-memory property not set");
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return;
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}
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address_space_init(&s->source_as, s->source_memory, "bitband-source");
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}
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/* Board init. */
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static const hwaddr bitband_input_addr[ARMV7M_NUM_BITBANDS] = {
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0x20000000, 0x40000000
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};
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static const hwaddr bitband_output_addr[ARMV7M_NUM_BITBANDS] = {
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0x22000000, 0x42000000
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};
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static MemTxResult v7m_sysreg_ns_write(void *opaque, hwaddr addr,
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uint64_t value, unsigned size,
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MemTxAttrs attrs)
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{
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MemoryRegion *mr = opaque;
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if (attrs.secure) {
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/* S accesses to the alias act like NS accesses to the real region */
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attrs.secure = 0;
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return memory_region_dispatch_write(mr, addr, value,
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size_memop(size) | MO_TE, attrs);
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} else {
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/* NS attrs are RAZ/WI for privileged, and BusFault for user */
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if (attrs.user) {
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return MEMTX_ERROR;
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}
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return MEMTX_OK;
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}
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}
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static MemTxResult v7m_sysreg_ns_read(void *opaque, hwaddr addr,
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uint64_t *data, unsigned size,
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MemTxAttrs attrs)
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{
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MemoryRegion *mr = opaque;
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if (attrs.secure) {
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/* S accesses to the alias act like NS accesses to the real region */
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attrs.secure = 0;
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return memory_region_dispatch_read(mr, addr, data,
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size_memop(size) | MO_TE, attrs);
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} else {
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/* NS attrs are RAZ/WI for privileged, and BusFault for user */
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if (attrs.user) {
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return MEMTX_ERROR;
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}
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*data = 0;
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return MEMTX_OK;
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}
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}
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static const MemoryRegionOps v7m_sysreg_ns_ops = {
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.read_with_attrs = v7m_sysreg_ns_read,
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.write_with_attrs = v7m_sysreg_ns_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static MemTxResult v7m_systick_write(void *opaque, hwaddr addr,
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uint64_t value, unsigned size,
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MemTxAttrs attrs)
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{
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ARMv7MState *s = opaque;
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MemoryRegion *mr;
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/* Direct the access to the correct systick */
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mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->systick[attrs.secure]), 0);
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return memory_region_dispatch_write(mr, addr, value,
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size_memop(size) | MO_TE, attrs);
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}
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static MemTxResult v7m_systick_read(void *opaque, hwaddr addr,
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uint64_t *data, unsigned size,
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MemTxAttrs attrs)
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{
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ARMv7MState *s = opaque;
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MemoryRegion *mr;
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/* Direct the access to the correct systick */
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mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->systick[attrs.secure]), 0);
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return memory_region_dispatch_read(mr, addr, data, size_memop(size) | MO_TE,
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attrs);
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}
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static const MemoryRegionOps v7m_systick_ops = {
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.read_with_attrs = v7m_systick_read,
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.write_with_attrs = v7m_systick_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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/*
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* Unassigned portions of the PPB space are RAZ/WI for privileged
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* accesses, and fault for non-privileged accesses.
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*/
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static MemTxResult ppb_default_read(void *opaque, hwaddr addr,
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uint64_t *data, unsigned size,
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MemTxAttrs attrs)
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{
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qemu_log_mask(LOG_UNIMP, "Read of unassigned area of PPB: offset 0x%x\n",
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(uint32_t)addr);
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if (attrs.user) {
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return MEMTX_ERROR;
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}
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*data = 0;
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return MEMTX_OK;
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}
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static MemTxResult ppb_default_write(void *opaque, hwaddr addr,
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uint64_t value, unsigned size,
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MemTxAttrs attrs)
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{
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qemu_log_mask(LOG_UNIMP, "Write of unassigned area of PPB: offset 0x%x\n",
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(uint32_t)addr);
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if (attrs.user) {
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return MEMTX_ERROR;
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}
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return MEMTX_OK;
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}
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static const MemoryRegionOps ppb_default_ops = {
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.read_with_attrs = ppb_default_read,
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.write_with_attrs = ppb_default_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid.min_access_size = 1,
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.valid.max_access_size = 8,
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};
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static void armv7m_instance_init(Object *obj)
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{
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ARMv7MState *s = ARMV7M(obj);
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int i;
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/* Can't init the cpu here, we don't yet know which model to use */
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memory_region_init(&s->container, obj, "armv7m-container", UINT64_MAX);
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object_initialize_child(obj, "nvic", &s->nvic, TYPE_NVIC);
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object_property_add_alias(obj, "num-irq",
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OBJECT(&s->nvic), "num-irq");
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object_property_add_alias(obj, "num-prio-bits",
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OBJECT(&s->nvic), "num-prio-bits");
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object_initialize_child(obj, "systick-reg-ns", &s->systick[M_REG_NS],
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TYPE_SYSTICK);
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/*
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* We can't initialize the secure systick here, as we don't know
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* yet if we need it.
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*/
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for (i = 0; i < ARRAY_SIZE(s->bitband); i++) {
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object_initialize_child(obj, "bitband[*]", &s->bitband[i],
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TYPE_BITBAND);
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}
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s->refclk = qdev_init_clock_in(DEVICE(obj), "refclk", NULL, NULL, 0);
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s->cpuclk = qdev_init_clock_in(DEVICE(obj), "cpuclk", NULL, NULL, 0);
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}
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static void armv7m_realize(DeviceState *dev, Error **errp)
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{
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ARMv7MState *s = ARMV7M(dev);
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SysBusDevice *sbd;
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Error *err = NULL;
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int i;
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if (!s->board_memory) {
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error_setg(errp, "memory property was not set");
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return;
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}
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/* cpuclk must be connected; refclk is optional */
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if (!clock_has_source(s->cpuclk)) {
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error_setg(errp, "armv7m: cpuclk must be connected");
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return;
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}
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memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -1);
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s->cpu = ARM_CPU(object_new_with_props(s->cpu_type, OBJECT(s), "cpu",
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&err, NULL));
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if (err != NULL) {
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error_propagate(errp, err);
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return;
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}
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object_property_set_link(OBJECT(s->cpu), "memory", OBJECT(&s->container),
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&error_abort);
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if (object_property_find(OBJECT(s->cpu), "idau")) {
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object_property_set_link(OBJECT(s->cpu), "idau", s->idau,
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&error_abort);
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}
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if (object_property_find(OBJECT(s->cpu), "init-svtor")) {
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if (!object_property_set_uint(OBJECT(s->cpu), "init-svtor",
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s->init_svtor, errp)) {
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return;
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}
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}
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if (object_property_find(OBJECT(s->cpu), "init-nsvtor")) {
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if (!object_property_set_uint(OBJECT(s->cpu), "init-nsvtor",
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s->init_nsvtor, errp)) {
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return;
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}
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}
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if (object_property_find(OBJECT(s->cpu), "vfp")) {
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if (!object_property_set_bool(OBJECT(s->cpu), "vfp", s->vfp, errp)) {
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return;
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}
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}
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if (object_property_find(OBJECT(s->cpu), "dsp")) {
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if (!object_property_set_bool(OBJECT(s->cpu), "dsp", s->dsp, errp)) {
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return;
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}
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}
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object_property_set_bool(OBJECT(s->cpu), "start-powered-off",
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s->start_powered_off, &error_abort);
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/*
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* Real M-profile hardware can be configured with a different number of
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* MPU regions for Secure vs NonSecure. QEMU's CPU implementation doesn't
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* support that yet, so catch attempts to select that.
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*/
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if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY) &&
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s->mpu_ns_regions != s->mpu_s_regions) {
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error_setg(errp,
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"mpu-ns-regions and mpu-s-regions properties must have the same value");
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return;
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}
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if (s->mpu_ns_regions != UINT_MAX &&
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object_property_find(OBJECT(s->cpu), "pmsav7-dregion")) {
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if (!object_property_set_uint(OBJECT(s->cpu), "pmsav7-dregion",
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s->mpu_ns_regions, errp)) {
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return;
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}
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}
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/*
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* Tell the CPU where the NVIC is; it will fail realize if it doesn't
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* have one. Similarly, tell the NVIC where its CPU is.
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*/
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s->cpu->env.nvic = &s->nvic;
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s->nvic.cpu = s->cpu;
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if (!qdev_realize(DEVICE(s->cpu), NULL, errp)) {
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return;
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}
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/* Note that we must realize the NVIC after the CPU */
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->nvic), errp)) {
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return;
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}
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/* Alias the NVIC's input and output GPIOs as our own so the board
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* code can wire them up. (We do this in realize because the
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* NVIC doesn't create the input GPIO array until realize.)
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*/
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qdev_pass_gpios(DEVICE(&s->nvic), dev, NULL);
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qdev_pass_gpios(DEVICE(&s->nvic), dev, "SYSRESETREQ");
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qdev_pass_gpios(DEVICE(&s->nvic), dev, "NMI");
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/*
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* We map various devices into the container MR at their architected
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* addresses. In particular, we map everything corresponding to the
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* "System PPB" space. This is the range from 0xe0000000 to 0xe00fffff
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* and includes the NVIC, the System Control Space (system registers),
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* the systick timer, and for CPUs with the Security extension an NS
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* banked version of all of these.
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*
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* The default behaviour for unimplemented registers/ranges
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* (for instance the Data Watchpoint and Trace unit at 0xe0001000)
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* is to RAZ/WI for privileged access and BusFault for non-privileged
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* access.
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*
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* The NVIC and System Control Space (SCS) starts at 0xe000e000
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* and looks like this:
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* 0x004 - ICTR
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* 0x010 - 0xff - systick
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* 0x100..0x7ec - NVIC
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* 0x7f0..0xcff - Reserved
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* 0xd00..0xd3c - SCS registers
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* 0xd40..0xeff - Reserved or Not implemented
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* 0xf00 - STIR
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*
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* Some registers within this space are banked between security states.
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* In v8M there is a second range 0xe002e000..0xe002efff which is the
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* NonSecure alias SCS; secure accesses to this behave like NS accesses
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* to the main SCS range, and non-secure accesses (including when
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* the security extension is not implemented) are RAZ/WI.
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* Note that both the main SCS range and the alias range are defined
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* to be exempt from memory attribution (R_BLJT) and so the memory
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* transaction attribute always matches the current CPU security
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* state (attrs.secure == env->v7m.secure). In the v7m_sysreg_ns_ops
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* wrappers we change attrs.secure to indicate the NS access; so
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* generally code determining which banked register to use should
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* use attrs.secure; code determining actual behaviour of the system
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* should use env->v7m.secure.
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*
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* Within the PPB space, some MRs overlap, and the priority
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* of overlapping regions is:
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* - default region (for RAZ/WI and BusFault) : -1
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* - system register regions (provided by the NVIC) : 0
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* - systick : 1
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* This is because the systick device is a small block of registers
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* in the middle of the other system control registers.
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*/
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memory_region_init_io(&s->defaultmem, OBJECT(s), &ppb_default_ops, s,
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"nvic-default", 0x100000);
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memory_region_add_subregion_overlap(&s->container, 0xe0000000,
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&s->defaultmem, -1);
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/* Wire the NVIC up to the CPU */
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sbd = SYS_BUS_DEVICE(&s->nvic);
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sysbus_connect_irq(sbd, 0,
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qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ));
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memory_region_add_subregion(&s->container, 0xe000e000,
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sysbus_mmio_get_region(sbd, 0));
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if (arm_feature(&s->cpu->env, ARM_FEATURE_V8)) {
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/* Create the NS alias region for the NVIC sysregs */
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memory_region_init_io(&s->sysreg_ns_mem, OBJECT(s),
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&v7m_sysreg_ns_ops,
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sysbus_mmio_get_region(sbd, 0),
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"nvic_sysregs_ns", 0x1000);
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memory_region_add_subregion(&s->container, 0xe002e000,
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&s->sysreg_ns_mem);
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}
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/*
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* Create and map the systick devices. Note that we only connect
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* refclk if it has been connected to us; otherwise the systick
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* device gets the wrong answer for clock_has_source(refclk), because
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* it has an immediate source (the ARMv7M's clock object) but not
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* an ultimate source, and then it won't correctly auto-select the
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* CPU clock as its only possible clock source.
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*/
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if (clock_has_source(s->refclk)) {
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qdev_connect_clock_in(DEVICE(&s->systick[M_REG_NS]), "refclk",
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s->refclk);
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}
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qdev_connect_clock_in(DEVICE(&s->systick[M_REG_NS]), "cpuclk", s->cpuclk);
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->systick[M_REG_NS]), errp)) {
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return;
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}
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->systick[M_REG_NS]), 0,
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qdev_get_gpio_in_named(DEVICE(&s->nvic),
|
|
"systick-trigger", M_REG_NS));
|
|
|
|
if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY)) {
|
|
/*
|
|
* We couldn't init the secure systick device in instance_init
|
|
* as we didn't know then if the CPU had the security extensions;
|
|
* so we have to do it here.
|
|
*/
|
|
object_initialize_child(OBJECT(dev), "systick-reg-s",
|
|
&s->systick[M_REG_S], TYPE_SYSTICK);
|
|
if (clock_has_source(s->refclk)) {
|
|
qdev_connect_clock_in(DEVICE(&s->systick[M_REG_S]), "refclk",
|
|
s->refclk);
|
|
}
|
|
qdev_connect_clock_in(DEVICE(&s->systick[M_REG_S]), "cpuclk",
|
|
s->cpuclk);
|
|
|
|
if (!sysbus_realize(SYS_BUS_DEVICE(&s->systick[M_REG_S]), errp)) {
|
|
return;
|
|
}
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->systick[M_REG_S]), 0,
|
|
qdev_get_gpio_in_named(DEVICE(&s->nvic),
|
|
"systick-trigger", M_REG_S));
|
|
}
|
|
|
|
memory_region_init_io(&s->systickmem, OBJECT(s),
|
|
&v7m_systick_ops, s,
|
|
"v7m_systick", 0xe0);
|
|
|
|
memory_region_add_subregion_overlap(&s->container, 0xe000e010,
|
|
&s->systickmem, 1);
|
|
if (arm_feature(&s->cpu->env, ARM_FEATURE_V8)) {
|
|
memory_region_init_io(&s->systick_ns_mem, OBJECT(s),
|
|
&v7m_sysreg_ns_ops, &s->systickmem,
|
|
"v7m_systick_ns", 0xe0);
|
|
memory_region_add_subregion_overlap(&s->container, 0xe002e010,
|
|
&s->systick_ns_mem, 1);
|
|
}
|
|
|
|
/* If the CPU has RAS support, create the RAS register block */
|
|
if (cpu_isar_feature(aa32_ras, s->cpu)) {
|
|
object_initialize_child(OBJECT(dev), "armv7m-ras",
|
|
&s->ras, TYPE_ARMV7M_RAS);
|
|
sbd = SYS_BUS_DEVICE(&s->ras);
|
|
if (!sysbus_realize(sbd, errp)) {
|
|
return;
|
|
}
|
|
memory_region_add_subregion_overlap(&s->container, 0xe0005000,
|
|
sysbus_mmio_get_region(sbd, 0), 1);
|
|
}
|
|
|
|
for (i = 0; i < ARRAY_SIZE(s->bitband); i++) {
|
|
if (s->enable_bitband) {
|
|
Object *obj = OBJECT(&s->bitband[i]);
|
|
sbd = SYS_BUS_DEVICE(&s->bitband[i]);
|
|
|
|
if (!object_property_set_int(obj, "base",
|
|
bitband_input_addr[i], errp)) {
|
|
return;
|
|
}
|
|
object_property_set_link(obj, "source-memory",
|
|
OBJECT(s->board_memory), &error_abort);
|
|
if (!sysbus_realize(SYS_BUS_DEVICE(obj), errp)) {
|
|
return;
|
|
}
|
|
|
|
memory_region_add_subregion(&s->container, bitband_output_addr[i],
|
|
sysbus_mmio_get_region(sbd, 0));
|
|
} else {
|
|
object_unparent(OBJECT(&s->bitband[i]));
|
|
}
|
|
}
|
|
}
|
|
|
|
static Property armv7m_properties[] = {
|
|
DEFINE_PROP_STRING("cpu-type", ARMv7MState, cpu_type),
|
|
DEFINE_PROP_LINK("memory", ARMv7MState, board_memory, TYPE_MEMORY_REGION,
|
|
MemoryRegion *),
|
|
DEFINE_PROP_LINK("idau", ARMv7MState, idau, TYPE_IDAU_INTERFACE, Object *),
|
|
DEFINE_PROP_UINT32("init-svtor", ARMv7MState, init_svtor, 0),
|
|
DEFINE_PROP_UINT32("init-nsvtor", ARMv7MState, init_nsvtor, 0),
|
|
DEFINE_PROP_BOOL("enable-bitband", ARMv7MState, enable_bitband, false),
|
|
DEFINE_PROP_BOOL("start-powered-off", ARMv7MState, start_powered_off,
|
|
false),
|
|
DEFINE_PROP_BOOL("vfp", ARMv7MState, vfp, true),
|
|
DEFINE_PROP_BOOL("dsp", ARMv7MState, dsp, true),
|
|
DEFINE_PROP_UINT32("mpu-ns-regions", ARMv7MState, mpu_ns_regions, UINT_MAX),
|
|
DEFINE_PROP_UINT32("mpu-s-regions", ARMv7MState, mpu_s_regions, UINT_MAX),
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
};
|
|
|
|
static const VMStateDescription vmstate_armv7m = {
|
|
.name = "armv7m",
|
|
.version_id = 1,
|
|
.minimum_version_id = 1,
|
|
.fields = (const VMStateField[]) {
|
|
VMSTATE_CLOCK(refclk, ARMv7MState),
|
|
VMSTATE_CLOCK(cpuclk, ARMv7MState),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
static void armv7m_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
dc->realize = armv7m_realize;
|
|
dc->vmsd = &vmstate_armv7m;
|
|
device_class_set_props(dc, armv7m_properties);
|
|
}
|
|
|
|
static const TypeInfo armv7m_info = {
|
|
.name = TYPE_ARMV7M,
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
.instance_size = sizeof(ARMv7MState),
|
|
.instance_init = armv7m_instance_init,
|
|
.class_init = armv7m_class_init,
|
|
};
|
|
|
|
static void armv7m_reset(void *opaque)
|
|
{
|
|
ARMCPU *cpu = opaque;
|
|
|
|
cpu_reset(CPU(cpu));
|
|
}
|
|
|
|
void armv7m_load_kernel(ARMCPU *cpu, const char *kernel_filename,
|
|
hwaddr mem_base, int mem_size)
|
|
{
|
|
ssize_t image_size;
|
|
uint64_t entry;
|
|
AddressSpace *as;
|
|
int asidx;
|
|
CPUState *cs = CPU(cpu);
|
|
|
|
if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) {
|
|
asidx = ARMASIdx_S;
|
|
} else {
|
|
asidx = ARMASIdx_NS;
|
|
}
|
|
as = cpu_get_address_space(cs, asidx);
|
|
|
|
if (kernel_filename) {
|
|
image_size = load_elf_as(kernel_filename, NULL, NULL, NULL,
|
|
&entry, NULL, NULL,
|
|
NULL, 0, EM_ARM, 1, 0, as);
|
|
if (image_size < 0) {
|
|
image_size = load_image_targphys_as(kernel_filename, mem_base,
|
|
mem_size, as);
|
|
}
|
|
if (image_size < 0) {
|
|
error_report("Could not load kernel '%s'", kernel_filename);
|
|
exit(1);
|
|
}
|
|
}
|
|
|
|
/* CPU objects (unlike devices) are not automatically reset on system
|
|
* reset, so we must always register a handler to do so. Unlike
|
|
* A-profile CPUs, we don't need to do anything special in the
|
|
* handler to arrange that it starts correctly.
|
|
* This is arguably the wrong place to do this, but it matches the
|
|
* way A-profile does it. Note that this means that every M profile
|
|
* board must call this function!
|
|
*/
|
|
qemu_register_reset(armv7m_reset, cpu);
|
|
}
|
|
|
|
static Property bitband_properties[] = {
|
|
DEFINE_PROP_UINT32("base", BitBandState, base, 0),
|
|
DEFINE_PROP_LINK("source-memory", BitBandState, source_memory,
|
|
TYPE_MEMORY_REGION, MemoryRegion *),
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
};
|
|
|
|
static void bitband_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
dc->realize = bitband_realize;
|
|
device_class_set_props(dc, bitband_properties);
|
|
}
|
|
|
|
static const TypeInfo bitband_info = {
|
|
.name = TYPE_BITBAND,
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
.instance_size = sizeof(BitBandState),
|
|
.instance_init = bitband_init,
|
|
.class_init = bitband_class_init,
|
|
};
|
|
|
|
static void armv7m_register_types(void)
|
|
{
|
|
type_register_static(&bitband_info);
|
|
type_register_static(&armv7m_info);
|
|
}
|
|
|
|
type_init(armv7m_register_types)
|