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234 lines
8.5 KiB
C
234 lines
8.5 KiB
C
/*
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* Allwinner A10 SoC emulation
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*
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* Copyright (C) 2013 Li Guang
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* Written by Li Guang <lig.fnst@cn.fujitsu.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "qemu/error-report.h"
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#include "qemu/module.h"
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#include "hw/char/serial-mm.h"
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#include "hw/sysbus.h"
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#include "hw/arm/allwinner-a10.h"
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#include "hw/misc/unimp.h"
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#include "sysemu/sysemu.h"
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#include "hw/boards.h"
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#include "hw/usb/hcd-ohci.h"
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#include "hw/loader.h"
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#include "target/arm/cpu-qom.h"
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#define AW_A10_SRAM_A_BASE 0x00000000
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#define AW_A10_DRAMC_BASE 0x01c01000
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#define AW_A10_MMC0_BASE 0x01c0f000
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#define AW_A10_CCM_BASE 0x01c20000
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#define AW_A10_PIC_REG_BASE 0x01c20400
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#define AW_A10_PIT_REG_BASE 0x01c20c00
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#define AW_A10_UART0_REG_BASE 0x01c28000
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#define AW_A10_SPI0_BASE 0x01c05000
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#define AW_A10_EMAC_BASE 0x01c0b000
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#define AW_A10_EHCI_BASE 0x01c14000
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#define AW_A10_OHCI_BASE 0x01c14400
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#define AW_A10_SATA_BASE 0x01c18000
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#define AW_A10_WDT_BASE 0x01c20c90
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#define AW_A10_RTC_BASE 0x01c20d00
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#define AW_A10_I2C0_BASE 0x01c2ac00
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void allwinner_a10_bootrom_setup(AwA10State *s, BlockBackend *blk)
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{
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const int64_t rom_size = 32 * KiB;
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g_autofree uint8_t *buffer = g_new0(uint8_t, rom_size);
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if (blk_pread(blk, 8 * KiB, rom_size, buffer, 0) < 0) {
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error_report("%s: failed to read BlockBackend data", __func__);
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exit(1);
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}
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rom_add_blob("allwinner-a10.bootrom", buffer, rom_size,
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rom_size, AW_A10_SRAM_A_BASE,
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NULL, NULL, NULL, NULL, false);
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}
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static void aw_a10_init(Object *obj)
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{
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AwA10State *s = AW_A10(obj);
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object_initialize_child(obj, "cpu", &s->cpu,
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ARM_CPU_TYPE_NAME("cortex-a8"));
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object_initialize_child(obj, "intc", &s->intc, TYPE_AW_A10_PIC);
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object_initialize_child(obj, "timer", &s->timer, TYPE_AW_A10_PIT);
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object_initialize_child(obj, "ccm", &s->ccm, TYPE_AW_A10_CCM);
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object_initialize_child(obj, "dramc", &s->dramc, TYPE_AW_A10_DRAMC);
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object_initialize_child(obj, "emac", &s->emac, TYPE_AW_EMAC);
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object_initialize_child(obj, "sata", &s->sata, TYPE_ALLWINNER_AHCI);
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object_initialize_child(obj, "i2c0", &s->i2c0, TYPE_AW_I2C);
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object_initialize_child(obj, "spi0", &s->spi0, TYPE_AW_A10_SPI);
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for (size_t i = 0; i < AW_A10_NUM_USB; i++) {
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object_initialize_child(obj, "ehci[*]", &s->ehci[i],
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TYPE_PLATFORM_EHCI);
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object_initialize_child(obj, "ohci[*]", &s->ohci[i], TYPE_SYSBUS_OHCI);
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}
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object_initialize_child(obj, "mmc0", &s->mmc0, TYPE_AW_SDHOST_SUN4I);
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object_initialize_child(obj, "rtc", &s->rtc, TYPE_AW_RTC_SUN4I);
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object_initialize_child(obj, "wdt", &s->wdt, TYPE_AW_WDT_SUN4I);
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}
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static void aw_a10_realize(DeviceState *dev, Error **errp)
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{
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AwA10State *s = AW_A10(dev);
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SysBusDevice *sysbusdev;
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if (!qdev_realize(DEVICE(&s->cpu), NULL, errp)) {
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return;
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}
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->intc), errp)) {
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return;
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}
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sysbusdev = SYS_BUS_DEVICE(&s->intc);
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sysbus_mmio_map(sysbusdev, 0, AW_A10_PIC_REG_BASE);
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sysbus_connect_irq(sysbusdev, 0,
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qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
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sysbus_connect_irq(sysbusdev, 1,
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qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
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qdev_pass_gpios(DEVICE(&s->intc), dev, NULL);
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer), errp)) {
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return;
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}
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sysbusdev = SYS_BUS_DEVICE(&s->timer);
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sysbus_mmio_map(sysbusdev, 0, AW_A10_PIT_REG_BASE);
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sysbus_connect_irq(sysbusdev, 0, qdev_get_gpio_in(dev, 22));
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sysbus_connect_irq(sysbusdev, 1, qdev_get_gpio_in(dev, 23));
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sysbus_connect_irq(sysbusdev, 2, qdev_get_gpio_in(dev, 24));
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sysbus_connect_irq(sysbusdev, 3, qdev_get_gpio_in(dev, 25));
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sysbus_connect_irq(sysbusdev, 4, qdev_get_gpio_in(dev, 67));
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sysbus_connect_irq(sysbusdev, 5, qdev_get_gpio_in(dev, 68));
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memory_region_init_ram(&s->sram_a, OBJECT(dev), "sram A", 48 * KiB,
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&error_fatal);
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memory_region_add_subregion(get_system_memory(), 0x00000000, &s->sram_a);
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create_unimplemented_device("a10-sram-ctrl", 0x01c00000, 4 * KiB);
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/* Clock Control Module */
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sysbus_realize(SYS_BUS_DEVICE(&s->ccm), &error_fatal);
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, AW_A10_CCM_BASE);
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/* DRAM Control Module */
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sysbus_realize(SYS_BUS_DEVICE(&s->dramc), &error_fatal);
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 0, AW_A10_DRAMC_BASE);
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qemu_configure_nic_device(DEVICE(&s->emac), true, NULL);
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->emac), errp)) {
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return;
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}
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sysbusdev = SYS_BUS_DEVICE(&s->emac);
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sysbus_mmio_map(sysbusdev, 0, AW_A10_EMAC_BASE);
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sysbus_connect_irq(sysbusdev, 0, qdev_get_gpio_in(dev, 55));
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->sata), errp)) {
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, AW_A10_SATA_BASE);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, qdev_get_gpio_in(dev, 56));
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/* FIXME use a qdev chardev prop instead of serial_hd() */
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serial_mm_init(get_system_memory(), AW_A10_UART0_REG_BASE, 2,
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qdev_get_gpio_in(dev, 1),
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115200, serial_hd(0), DEVICE_NATIVE_ENDIAN);
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for (size_t i = 0; i < AW_A10_NUM_USB; i++) {
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g_autofree char *bus = g_strdup_printf("usb-bus.%zu", i);
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object_property_set_bool(OBJECT(&s->ehci[i]), "companion-enable",
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true, &error_fatal);
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sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), &error_fatal);
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0,
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AW_A10_EHCI_BASE + i * 0x8000);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0,
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qdev_get_gpio_in(dev, 39 + i));
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object_property_set_str(OBJECT(&s->ohci[i]), "masterbus", bus,
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&error_fatal);
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sysbus_realize(SYS_BUS_DEVICE(&s->ohci[i]), &error_fatal);
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->ohci[i]), 0,
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AW_A10_OHCI_BASE + i * 0x8000);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->ohci[i]), 0,
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qdev_get_gpio_in(dev, 64 + i));
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}
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/* SD/MMC */
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object_property_set_link(OBJECT(&s->mmc0), "dma-memory",
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OBJECT(get_system_memory()), &error_fatal);
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sysbus_realize(SYS_BUS_DEVICE(&s->mmc0), &error_fatal);
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc0), 0, AW_A10_MMC0_BASE);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc0), 0, qdev_get_gpio_in(dev, 32));
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object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->mmc0),
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"sd-bus");
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/* RTC */
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sysbus_realize(SYS_BUS_DEVICE(&s->rtc), &error_fatal);
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sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->rtc), 0, AW_A10_RTC_BASE, 10);
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/* I2C */
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sysbus_realize(SYS_BUS_DEVICE(&s->i2c0), &error_fatal);
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c0), 0, AW_A10_I2C0_BASE);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c0), 0, qdev_get_gpio_in(dev, 7));
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/* SPI */
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sysbus_realize(SYS_BUS_DEVICE(&s->spi0), &error_fatal);
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi0), 0, AW_A10_SPI0_BASE);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi0), 0, qdev_get_gpio_in(dev, 10));
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/* WDT */
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sysbus_realize(SYS_BUS_DEVICE(&s->wdt), &error_fatal);
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sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->wdt), 0, AW_A10_WDT_BASE, 1);
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}
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static void aw_a10_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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dc->realize = aw_a10_realize;
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/* Reason: Uses serial_hds and nd_table in realize function */
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dc->user_creatable = false;
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}
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static const TypeInfo aw_a10_type_info = {
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.name = TYPE_AW_A10,
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.parent = TYPE_DEVICE,
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.instance_size = sizeof(AwA10State),
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.instance_init = aw_a10_init,
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.class_init = aw_a10_class_init,
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};
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static void aw_a10_register_types(void)
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{
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type_register_static(&aw_a10_type_info);
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}
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type_init(aw_a10_register_types)
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