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Djordje Todorovic 2264f637da hw/riscv: Add support for MIPS Boston-aia board mode ... The board model supports up to 64 harts with MIPS CPS, MIPS GCR, MIPS CPC, AIA plic, and AIA clint devices. The model can create boot code, if there is no -bios parameter. We can specify -smp x, cores=y,thread=z. Ex: Use 4 cores and 2 threads with each core to have 8 smp cpus as follows. qemu-system-riscv64 -cpu mips-p8700 \ -m 2G -M boston-aia \ -smp 8,cores=4,threads=2 -kernel fw_payload.bin \ -drive file=rootfs.ext2,format=raw -serial stdio Signed-off-by: Chao-ying Fu <cfu@mips.com> Signed-off-by: Djordje Todorovic <djordje.todorovic@htecgroup.com> Acked-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20260108134128.2218102-11-djordje.todorovic@htecgroup.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		6 days ago
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microblaze-v-generic.rst	hw/riscv: Add Microblaze V generic board	1 year ago
microchip-icicle-kit.rst	hw/riscv: microchip_pfsoc: Rework documentation	8 months ago
mips.rst	hw/riscv: Add support for MIPS Boston-aia board mode	6 days ago
shakti-c.rst	Fix some typos in documentation (found by codespell)	4 years ago
sifive_u.rst	docs/system/riscv: sifive_u: Update S-mode U-Boot image build instructions	2 years ago
virt.rst	docs: update riscv/virt.rst with kernel-irqchip=split support	1 year ago
xiangshan-kunminghu.rst	hw/riscv: Initial support for BOSC's Xiangshan Kunminghu FPGA prototype	6 months ago