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139 lines
7.1 KiB
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Booting from real channel-attached devices on s390x
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===================================================
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s390 hardware IPL
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-----------------
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The s390 hardware IPL process consists of the following steps.
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1. A READ IPL ccw is constructed in memory location ``0x0``.
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This ccw, by definition, reads the IPL1 record which is located on the disk
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at cylinder 0 track 0 record 1. Note that the chain flag is on in this ccw
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so when it is complete another ccw will be fetched and executed from memory
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location ``0x08``.
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2. Execute the Read IPL ccw at ``0x00``, thereby reading IPL1 data into ``0x00``.
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IPL1 data is 24 bytes in length and consists of the following pieces of
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information: ``[psw][read ccw][tic ccw]``. When the machine executes the Read
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IPL ccw it read the 24-bytes of IPL1 to be read into memory starting at
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location ``0x0``. Then the ccw program at ``0x08`` which consists of a read
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ccw and a tic ccw is automatically executed because of the chain flag from
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the original READ IPL ccw. The read ccw will read the IPL2 data into memory
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and the TIC (Transfer In Channel) will transfer control to the channel
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program contained in the IPL2 data. The TIC channel command is the
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equivalent of a branch/jump/goto instruction for channel programs.
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NOTE: The ccws in IPL1 are defined by the architecture to be format 0.
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3. Execute IPL2.
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The TIC ccw instruction at the end of the IPL1 channel program will begin
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the execution of the IPL2 channel program. IPL2 is stage-2 of the boot
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process and will contain a larger channel program than IPL1. The point of
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IPL2 is to find and load either the operating system or a small program that
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loads the operating system from disk. At the end of this step all or some of
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the real operating system is loaded into memory and we are ready to hand
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control over to the guest operating system. At this point the guest
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operating system is entirely responsible for loading any more data it might
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need to function.
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NOTE: The IPL2 channel program might read data into memory
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location ``0x0`` thereby overwriting the IPL1 psw and channel program. This is ok
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as long as the data placed in location ``0x0`` contains a psw whose instruction
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address points to the guest operating system code to execute at the end of
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the IPL/boot process.
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NOTE: The ccws in IPL2 are defined by the architecture to be format 0.
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4. Start executing the guest operating system.
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The psw that was loaded into memory location ``0x0`` as part of the ipl process
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should contain the needed flags for the operating system we have loaded. The
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psw's instruction address will point to the location in memory where we want
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to start executing the operating system. This psw is loaded (via LPSW
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instruction) causing control to be passed to the operating system code.
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In a non-virtualized environment this process, handled entirely by the hardware,
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is kicked off by the user initiating a "Load" procedure from the hardware
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management console. This "Load" procedure crafts a special "Read IPL" ccw in
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memory location 0x0 that reads IPL1. It then executes this ccw thereby kicking
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off the reading of IPL1 data. Since the channel program from IPL1 will be
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written immediately after the special "Read IPL" ccw, the IPL1 channel program
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will be executed immediately (the special read ccw has the chaining bit turned
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on). The TIC at the end of the IPL1 channel program will cause the IPL2 channel
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program to be executed automatically. After this sequence completes the "Load"
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procedure then loads the psw from ``0x0``.
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How this all pertains to QEMU (and the kernel)
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----------------------------------------------
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In theory we should merely have to do the following to IPL/boot a guest
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operating system from a DASD device:
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1. Place a "Read IPL" ccw into memory location ``0x0`` with chaining bit on.
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2. Execute channel program at ``0x0``.
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3. LPSW ``0x0``.
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However, our emulation of the machine's channel program logic within the kernel
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is missing one key feature that is required for this process to work:
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non-prefetch of ccw data.
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When we start a channel program we pass the channel subsystem parameters via an
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ORB (Operation Request Block). One of those parameters is a prefetch bit. If the
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bit is on then the vfio-ccw kernel driver is allowed to read the entire channel
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program from guest memory before it starts executing it. This means that any
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channel commands that read additional channel commands will not work as expected
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because the newly read commands will only exist in guest memory and NOT within
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the kernel's channel subsystem memory. The kernel vfio-ccw driver currently
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requires this bit to be on for all channel programs. This is a problem because
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the IPL process consists of transferring control from the "Read IPL" ccw
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immediately to the IPL1 channel program that was read by "Read IPL".
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Not being able to turn off prefetch will also prevent the TIC at the end of the
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IPL1 channel program from transferring control to the IPL2 channel program.
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Lastly, in some cases (the zipl bootloader for example) the IPL2 program also
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transfers control to another channel program segment immediately after reading
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it from the disk. So we need to be able to handle this case.
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What QEMU does
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--------------
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Since we are forced to live with prefetch we cannot use the very simple IPL
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procedure we defined in the preceding section. So we compensate by doing the
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following.
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1. Place "Read IPL" ccw into memory location ``0x0``, but turn off chaining bit.
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2. Execute "Read IPL" at ``0x0``.
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So now IPL1's psw is at ``0x0`` and IPL1's channel program is at ``0x08``.
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3. Write a custom channel program that will seek to the IPL2 record and then
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execute the READ and TIC ccws from IPL1. Normally the seek is not required
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because after reading the IPL1 record the disk is automatically positioned
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to read the very next record which will be IPL2. But since we are not reading
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both IPL1 and IPL2 as part of the same channel program we must manually set
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the position.
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4. Grab the target address of the TIC instruction from the IPL1 channel program.
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This address is where the IPL2 channel program starts.
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Now IPL2 is loaded into memory somewhere, and we know the address.
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5. Execute the IPL2 channel program at the address obtained in step #4.
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Because this channel program can be dynamic, we must use a special algorithm
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that detects a READ immediately followed by a TIC and breaks the ccw chain
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by turning off the chain bit in the READ ccw. When control is returned from
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the kernel/hardware to the QEMU bios code we immediately issue another start
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subchannel to execute the remaining TIC instruction. This causes the entire
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channel program (starting from the TIC) and all needed data to be refetched
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thereby stepping around the limitation that would otherwise prevent this
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channel program from executing properly.
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Now the operating system code is loaded somewhere in guest memory and the psw
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in memory location ``0x0`` will point to entry code for the guest operating
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system.
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6. LPSW ``0x0``
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LPSW transfers control to the guest operating system and we're done.
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