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310 lines
7.8 KiB
C
310 lines
7.8 KiB
C
/*
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* QEMU disassembler -- RISC-V specific header.
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#ifndef DISAS_RISCV_H
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#define DISAS_RISCV_H
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#include "target/riscv/cpu_cfg.h"
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/* types */
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typedef uint64_t rv_inst;
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typedef uint16_t rv_opcode;
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/* enums */
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typedef enum {
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rv32,
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rv64,
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rv128
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} rv_isa;
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typedef enum {
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rv_rm_rne = 0,
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rv_rm_rtz = 1,
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rv_rm_rdn = 2,
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rv_rm_rup = 3,
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rv_rm_rmm = 4,
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rv_rm_dyn = 7,
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} rv_rm;
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typedef enum {
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rv_fence_i = 8,
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rv_fence_o = 4,
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rv_fence_r = 2,
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rv_fence_w = 1,
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} rv_fence;
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typedef enum {
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rv_ireg_zero,
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rv_ireg_ra,
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rv_ireg_sp,
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rv_ireg_gp,
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rv_ireg_tp,
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rv_ireg_t0,
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rv_ireg_t1,
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rv_ireg_t2,
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rv_ireg_s0,
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rv_ireg_s1,
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rv_ireg_a0,
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rv_ireg_a1,
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rv_ireg_a2,
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rv_ireg_a3,
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rv_ireg_a4,
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rv_ireg_a5,
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rv_ireg_a6,
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rv_ireg_a7,
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rv_ireg_s2,
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rv_ireg_s3,
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rv_ireg_s4,
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rv_ireg_s5,
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rv_ireg_s6,
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rv_ireg_s7,
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rv_ireg_s8,
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rv_ireg_s9,
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rv_ireg_s10,
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rv_ireg_s11,
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rv_ireg_t3,
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rv_ireg_t4,
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rv_ireg_t5,
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rv_ireg_t6,
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} rv_ireg;
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typedef enum {
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rvc_end,
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rvc_rd_eq_ra,
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rvc_rd_eq_x0,
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rvc_rs1_eq_x0,
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rvc_rs2_eq_x0,
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rvc_rs2_eq_rs1,
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rvc_rs1_eq_ra,
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rvc_imm_eq_zero,
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rvc_imm_eq_n1,
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rvc_imm_eq_p1,
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rvc_csr_eq_0x001,
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rvc_csr_eq_0x002,
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rvc_csr_eq_0x003,
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rvc_csr_eq_0xc00,
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rvc_csr_eq_0xc01,
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rvc_csr_eq_0xc02,
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rvc_csr_eq_0xc80,
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rvc_csr_eq_0xc81,
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rvc_csr_eq_0xc82,
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} rvc_constraint;
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typedef enum {
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rv_codec_illegal,
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rv_codec_none,
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rv_codec_u,
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rv_codec_uj,
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rv_codec_i,
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rv_codec_i_sh5,
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rv_codec_i_sh6,
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rv_codec_i_sh7,
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rv_codec_i_csr,
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rv_codec_s,
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rv_codec_sb,
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rv_codec_r,
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rv_codec_r_m,
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rv_codec_r4_m,
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rv_codec_r_a,
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rv_codec_r_l,
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rv_codec_r_f,
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rv_codec_cb,
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rv_codec_cb_imm,
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rv_codec_cb_sh5,
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rv_codec_cb_sh6,
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rv_codec_ci,
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rv_codec_ci_sh5,
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rv_codec_ci_sh6,
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rv_codec_ci_16sp,
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rv_codec_ci_lwsp,
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rv_codec_ci_ldsp,
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rv_codec_ci_lqsp,
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rv_codec_ci_li,
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rv_codec_ci_lui,
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rv_codec_ci_none,
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rv_codec_ciw_4spn,
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rv_codec_cj,
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rv_codec_cj_jal,
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rv_codec_cl_lw,
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rv_codec_cl_ld,
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rv_codec_cl_lq,
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rv_codec_cr,
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rv_codec_cr_mv,
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rv_codec_cr_jalr,
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rv_codec_cr_jr,
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rv_codec_cs,
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rv_codec_cs_sw,
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rv_codec_cs_sd,
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rv_codec_cs_sq,
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rv_codec_css_swsp,
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rv_codec_css_sdsp,
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rv_codec_css_sqsp,
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rv_codec_k_bs,
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rv_codec_k_rnum,
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rv_codec_v_r,
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rv_codec_v_ldst,
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rv_codec_v_i,
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rv_codec_vsetvli,
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rv_codec_vsetivli,
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rv_codec_vror_vi,
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rv_codec_zcb_ext,
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rv_codec_zcb_mul,
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rv_codec_zcb_lb,
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rv_codec_zcb_lh,
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rv_codec_zcmp_cm_pushpop,
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rv_codec_zcmp_cm_mv,
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rv_codec_zcmt_jt,
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rv_codec_r2_imm5,
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rv_codec_r2,
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rv_codec_r2_imm6,
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rv_codec_r_imm2,
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rv_codec_r2_immhl,
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rv_codec_r2_imm2_imm5,
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rv_codec_fli,
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rv_codec_lp,
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rv_codec_cmop_ss,
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} rv_codec;
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/* structures */
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typedef struct {
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const int op;
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const rvc_constraint *constraints;
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} rv_comp_data;
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typedef struct {
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const char * const name;
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const rv_codec codec;
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const char * const format;
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const rv_comp_data *pseudo;
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const short decomp_rv32;
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const short decomp_rv64;
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const short decomp_rv128;
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const short decomp_data;
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} rv_opcode_data;
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typedef struct {
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RISCVCPUConfig *cfg;
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uint64_t pc;
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uint64_t inst;
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const rv_opcode_data *opcode_data;
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int32_t imm;
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int32_t imm1;
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uint16_t op;
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uint8_t codec;
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uint8_t rd;
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uint8_t rs1;
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uint8_t rs2;
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uint8_t rs3;
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uint8_t rm;
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uint8_t pred;
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uint8_t succ;
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uint8_t aq;
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uint8_t rl;
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uint8_t bs;
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uint8_t rnum;
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uint8_t vm;
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uint32_t vzimm;
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uint8_t rlist;
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} rv_decode;
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enum {
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rv_op_illegal = 0
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};
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enum {
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rvcd_imm_nz = 0x1
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};
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/* instruction formats */
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#define rv_fmt_none "O\t"
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#define rv_fmt_rs1 "O\t1"
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#define rv_fmt_rs2 "O\t2"
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#define rv_fmt_offset "O\to"
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#define rv_fmt_pred_succ "O\tp,s"
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#define rv_fmt_rs1_rs2 "O\t1,2"
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#define rv_fmt_rd_imm "O\t0,i"
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#define rv_fmt_rd_uimm "O\t0,Ui"
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#define rv_fmt_imm "O\ti"
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#define rv_fmt_rd_offset "O\t0,o"
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#define rv_fmt_rd_uoffset "O\t0,Uo"
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#define rv_fmt_rd_rs1_rs2 "O\t0,1,2"
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#define rv_fmt_frd_rs1 "O\t3,1"
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#define rv_fmt_frd_rs1_rs2 "O\t3,1,2"
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#define rv_fmt_frd_frs1 "O\t3,4"
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#define rv_fmt_rd_frs1 "O\t0,4"
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#define rv_fmt_rd_frs1_frs2 "O\t0,4,5"
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#define rv_fmt_frd_frs1_frs2 "O\t3,4,5"
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#define rv_fmt_rm_frd_frs1 "O\tr,3,4"
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#define rv_fmt_rm_frd_rs1 "O\tr,3,1"
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#define rv_fmt_rm_rd_frs1 "O\tr,0,4"
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#define rv_fmt_rm_frd_frs1_frs2 "O\tr,3,4,5"
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#define rv_fmt_rm_frd_frs1_frs2_frs3 "O\tr,3,4,5,6"
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#define rv_fmt_rd_rs1_imm "O\t0,1,i"
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#define rv_fmt_rd_rs1_offset "O\t0,1,i"
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#define rv_fmt_rd_offset_rs1 "O\t0,i(1)"
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#define rv_fmt_frd_offset_rs1 "O\t3,i(1)"
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#define rv_fmt_rd_csr_rs1 "O\t0,c,1"
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#define rv_fmt_rd_csr_zimm "O\t0,c,7"
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#define rv_fmt_rs2_offset_rs1 "O\t2,i(1)"
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#define rv_fmt_frs2_offset_rs1 "O\t5,i(1)"
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#define rv_fmt_rs1_rs2_offset "O\t1,2,o"
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#define rv_fmt_rs2_rs1_offset "O\t2,1,o"
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#define rv_fmt_aqrl_rd_rs2_rs1 "OAR\t0,2,(1)"
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#define rv_fmt_aqrl_rd_rs1 "OAR\t0,(1)"
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#define rv_fmt_rd "O\t0"
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#define rv_fmt_rd_zimm "O\t0,7"
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#define rv_fmt_rd_rs1 "O\t0,1"
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#define rv_fmt_rd_rs2 "O\t0,2"
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#define rv_fmt_rs1_offset "O\t1,o"
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#define rv_fmt_rs2_offset "O\t2,o"
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#define rv_fmt_rs1_rs2_bs "O\t1,2,b"
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#define rv_fmt_rd_rs1_rnum "O\t0,1,n"
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#define rv_fmt_ldst_vd_rs1_vm "O\tD,(1)m"
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#define rv_fmt_ldst_vd_rs1_rs2_vm "O\tD,(1),2m"
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#define rv_fmt_ldst_vd_rs1_vs2_vm "O\tD,(1),Fm"
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#define rv_fmt_vd_vs2_vs1 "O\tD,F,E"
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#define rv_fmt_vd_vs2_vs1_vl "O\tD,F,El"
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#define rv_fmt_vd_vs2_vs1_vm "O\tD,F,Em"
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#define rv_fmt_vd_vs2_rs1_vl "O\tD,F,1l"
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#define rv_fmt_vd_vs2_fs1_vl "O\tD,F,4l"
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#define rv_fmt_vd_vs2_rs1_vm "O\tD,F,1m"
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#define rv_fmt_vd_vs2_fs1_vm "O\tD,F,4m"
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#define rv_fmt_vd_vs2_imm_vl "O\tD,F,il"
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#define rv_fmt_vd_vs2_imm_vm "O\tD,F,im"
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#define rv_fmt_vd_vs2_uimm "O\tD,F,u"
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#define rv_fmt_vd_vs2_uimm_vm "O\tD,F,um"
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#define rv_fmt_vd_vs1_vs2_vm "O\tD,E,Fm"
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#define rv_fmt_vd_rs1_vs2_vm "O\tD,1,Fm"
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#define rv_fmt_vd_fs1_vs2_vm "O\tD,4,Fm"
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#define rv_fmt_vd_vs1 "O\tD,E"
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#define rv_fmt_vd_rs1 "O\tD,1"
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#define rv_fmt_vd_fs1 "O\tD,4"
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#define rv_fmt_vd_imm "O\tD,i"
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#define rv_fmt_vd_vs2 "O\tD,F"
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#define rv_fmt_vd_vs2_vm "O\tD,Fm"
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#define rv_fmt_rd_vs2_vm "O\t0,Fm"
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#define rv_fmt_rd_vs2 "O\t0,F"
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#define rv_fmt_fd_vs2 "O\t3,F"
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#define rv_fmt_vd_vm "O\tDm"
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#define rv_fmt_vsetvli "O\t0,1,v"
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#define rv_fmt_vsetivli "O\t0,i,v"
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#define rv_fmt_rs1_rs2_zce_ldst "O\t2,i(1)"
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#define rv_fmt_push_rlist "O\tx,-i"
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#define rv_fmt_pop_rlist "O\tx,i"
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#define rv_fmt_zcmt_index "O\ti"
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#define rv_fmt_rd_rs1_rs2_imm "O\t0,1,2,i"
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#define rv_fmt_frd_rs1_rs2_imm "O\t3,1,2,i"
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#define rv_fmt_rd_rs1_immh_imml "O\t0,1,i,j"
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#define rv_fmt_rd_rs1_immh_imml_addr "O\t0,(1),i,j"
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#define rv_fmt_rd2_imm "O\t0,2,(1),i"
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#define rv_fmt_fli "O\t3,h"
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#endif /* DISAS_RISCV_H */
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