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106 lines
4.9 KiB
C
106 lines
4.9 KiB
C
/*
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Copyright 2005-2014 Intel Corporation. All Rights Reserved.
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This file is part of Threading Building Blocks. Threading Building Blocks is free software;
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you can redistribute it and/or modify it under the terms of the GNU General Public License
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version 2 as published by the Free Software Foundation. Threading Building Blocks is
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distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the
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implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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See the GNU General Public License for more details. You should have received a copy of
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the GNU General Public License along with Threading Building Blocks; if not, write to the
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Free Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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As a special exception, you may use this file as part of a free software library without
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restriction. Specifically, if other files instantiate templates or use macros or inline
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functions from this file, or you compile this file and link it with other files to produce
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an executable, this file does not by itself cause the resulting executable to be covered
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by the GNU General Public License. This exception does not however invalidate any other
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reasons why the executable file might be covered by the GNU General Public License.
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*/
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#if !defined(__TBB_machine_H) || defined(__TBB_machine_windows_intel64_H)
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#error Do not #include this internal file directly; use public TBB headers instead.
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#endif
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#define __TBB_machine_windows_intel64_H
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#define __TBB_WORDSIZE 8
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#define __TBB_ENDIANNESS __TBB_ENDIAN_LITTLE
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#include <intrin.h>
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#include "msvc_ia32_common.h"
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//TODO: Use _InterlockedXXX16 intrinsics for 2 byte operations
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#if !__INTEL_COMPILER
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#pragma intrinsic(_InterlockedOr64)
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#pragma intrinsic(_InterlockedAnd64)
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#pragma intrinsic(_InterlockedCompareExchange)
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#pragma intrinsic(_InterlockedCompareExchange64)
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#pragma intrinsic(_InterlockedExchangeAdd)
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#pragma intrinsic(_InterlockedExchangeAdd64)
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#pragma intrinsic(_InterlockedExchange)
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#pragma intrinsic(_InterlockedExchange64)
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#endif /* !(__INTEL_COMPILER) */
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#if __INTEL_COMPILER && (__INTEL_COMPILER < 1100)
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#define __TBB_compiler_fence() __asm { __asm nop }
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#define __TBB_full_memory_fence() __asm { __asm mfence }
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#elif _MSC_VER >= 1300 || __INTEL_COMPILER
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#pragma intrinsic(_ReadWriteBarrier)
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#pragma intrinsic(_mm_mfence)
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#define __TBB_compiler_fence() _ReadWriteBarrier()
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#define __TBB_full_memory_fence() _mm_mfence()
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#endif
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#define __TBB_control_consistency_helper() __TBB_compiler_fence()
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#define __TBB_acquire_consistency_helper() __TBB_compiler_fence()
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#define __TBB_release_consistency_helper() __TBB_compiler_fence()
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// ATTENTION: if you ever change argument types in machine-specific primitives,
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// please take care of atomic_word<> specializations in tbb/atomic.h
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extern "C" {
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__int8 __TBB_EXPORTED_FUNC __TBB_machine_cmpswp1 (volatile void *ptr, __int8 value, __int8 comparand );
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__int8 __TBB_EXPORTED_FUNC __TBB_machine_fetchadd1 (volatile void *ptr, __int8 addend );
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__int8 __TBB_EXPORTED_FUNC __TBB_machine_fetchstore1 (volatile void *ptr, __int8 value );
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__int16 __TBB_EXPORTED_FUNC __TBB_machine_cmpswp2 (volatile void *ptr, __int16 value, __int16 comparand );
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__int16 __TBB_EXPORTED_FUNC __TBB_machine_fetchadd2 (volatile void *ptr, __int16 addend );
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__int16 __TBB_EXPORTED_FUNC __TBB_machine_fetchstore2 (volatile void *ptr, __int16 value );
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}
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inline long __TBB_machine_cmpswp4 (volatile void *ptr, __int32 value, __int32 comparand ) {
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return _InterlockedCompareExchange( (long*)ptr, value, comparand );
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}
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inline long __TBB_machine_fetchadd4 (volatile void *ptr, __int32 addend ) {
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return _InterlockedExchangeAdd( (long*)ptr, addend );
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}
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inline long __TBB_machine_fetchstore4 (volatile void *ptr, __int32 value ) {
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return _InterlockedExchange( (long*)ptr, value );
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}
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inline __int64 __TBB_machine_cmpswp8 (volatile void *ptr, __int64 value, __int64 comparand ) {
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return _InterlockedCompareExchange64( (__int64*)ptr, value, comparand );
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}
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inline __int64 __TBB_machine_fetchadd8 (volatile void *ptr, __int64 addend ) {
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return _InterlockedExchangeAdd64( (__int64*)ptr, addend );
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}
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inline __int64 __TBB_machine_fetchstore8 (volatile void *ptr, __int64 value ) {
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return _InterlockedExchange64( (__int64*)ptr, value );
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}
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#define __TBB_USE_FETCHSTORE_AS_FULL_FENCED_STORE 1
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#define __TBB_USE_GENERIC_HALF_FENCED_LOAD_STORE 1
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#define __TBB_USE_GENERIC_RELAXED_LOAD_STORE 1
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#define __TBB_USE_GENERIC_SEQUENTIAL_CONSISTENCY_LOAD_STORE 1
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inline void __TBB_machine_OR( volatile void *operand, intptr_t addend ) {
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_InterlockedOr64((__int64*)operand, addend);
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}
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inline void __TBB_machine_AND( volatile void *operand, intptr_t addend ) {
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_InterlockedAnd64((__int64*)operand, addend);
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}
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#define __TBB_AtomicOR(P,V) __TBB_machine_OR(P,V)
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#define __TBB_AtomicAND(P,V) __TBB_machine_AND(P,V)
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