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145 lines
5.3 KiB
C
145 lines
5.3 KiB
C
/*
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Copyright 2005-2014 Intel Corporation. All Rights Reserved.
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This file is part of Threading Building Blocks. Threading Building Blocks is free software;
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you can redistribute it and/or modify it under the terms of the GNU General Public License
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version 2 as published by the Free Software Foundation. Threading Building Blocks is
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distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the
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implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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See the GNU General Public License for more details. You should have received a copy of
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the GNU General Public License along with Threading Building Blocks; if not, write to the
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Free Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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As a special exception, you may use this file as part of a free software library without
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restriction. Specifically, if other files instantiate templates or use macros or inline
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functions from this file, or you compile this file and link it with other files to produce
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an executable, this file does not by itself cause the resulting executable to be covered
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by the GNU General Public License. This exception does not however invalidate any other
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reasons why the executable file might be covered by the GNU General Public License.
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*/
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#if !defined(__TBB_machine_H) || defined(__TBB_machine_windows_ia32_H)
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#error Do not #include this internal file directly; use public TBB headers instead.
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#endif
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#define __TBB_machine_windows_ia32_H
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#include "msvc_ia32_common.h"
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#define __TBB_WORDSIZE 4
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#define __TBB_ENDIANNESS __TBB_ENDIAN_LITTLE
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#if __INTEL_COMPILER && (__INTEL_COMPILER < 1100)
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#define __TBB_compiler_fence() __asm { __asm nop }
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#define __TBB_full_memory_fence() __asm { __asm mfence }
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#elif _MSC_VER >= 1300 || __INTEL_COMPILER
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#pragma intrinsic(_ReadWriteBarrier)
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#pragma intrinsic(_mm_mfence)
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#define __TBB_compiler_fence() _ReadWriteBarrier()
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#define __TBB_full_memory_fence() _mm_mfence()
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#else
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#error Unsupported compiler - need to define __TBB_{control,acquire,release}_consistency_helper to support it
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#endif
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#define __TBB_control_consistency_helper() __TBB_compiler_fence()
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#define __TBB_acquire_consistency_helper() __TBB_compiler_fence()
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#define __TBB_release_consistency_helper() __TBB_compiler_fence()
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#if defined(_MSC_VER) && !defined(__INTEL_COMPILER)
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// Workaround for overzealous compiler warnings in /Wp64 mode
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#pragma warning (push)
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#pragma warning (disable: 4244 4267)
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#endif
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extern "C" {
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__int64 __TBB_EXPORTED_FUNC __TBB_machine_cmpswp8 (volatile void *ptr, __int64 value, __int64 comparand );
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__int64 __TBB_EXPORTED_FUNC __TBB_machine_fetchadd8 (volatile void *ptr, __int64 addend );
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__int64 __TBB_EXPORTED_FUNC __TBB_machine_fetchstore8 (volatile void *ptr, __int64 value );
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void __TBB_EXPORTED_FUNC __TBB_machine_store8 (volatile void *ptr, __int64 value );
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__int64 __TBB_EXPORTED_FUNC __TBB_machine_load8 (const volatile void *ptr);
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}
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//TODO: use _InterlockedXXX intrinsics as they available since VC 2005
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#define __TBB_MACHINE_DEFINE_ATOMICS(S,T,U,A,C) \
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static inline T __TBB_machine_cmpswp##S ( volatile void * ptr, U value, U comparand ) { \
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T result; \
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volatile T *p = (T *)ptr; \
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__asm \
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{ \
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__asm mov edx, p \
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__asm mov C , value \
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__asm mov A , comparand \
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__asm lock cmpxchg [edx], C \
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__asm mov result, A \
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} \
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return result; \
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} \
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\
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static inline T __TBB_machine_fetchadd##S ( volatile void * ptr, U addend ) { \
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T result; \
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volatile T *p = (T *)ptr; \
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__asm \
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{ \
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__asm mov edx, p \
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__asm mov A, addend \
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__asm lock xadd [edx], A \
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__asm mov result, A \
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} \
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return result; \
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}\
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\
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static inline T __TBB_machine_fetchstore##S ( volatile void * ptr, U value ) { \
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T result; \
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volatile T *p = (T *)ptr; \
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__asm \
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{ \
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__asm mov edx, p \
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__asm mov A, value \
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__asm lock xchg [edx], A \
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__asm mov result, A \
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} \
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return result; \
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}
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__TBB_MACHINE_DEFINE_ATOMICS(1, __int8, __int8, al, cl)
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__TBB_MACHINE_DEFINE_ATOMICS(2, __int16, __int16, ax, cx)
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__TBB_MACHINE_DEFINE_ATOMICS(4, ptrdiff_t, ptrdiff_t, eax, ecx)
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#undef __TBB_MACHINE_DEFINE_ATOMICS
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static inline void __TBB_machine_OR( volatile void *operand, __int32 addend ) {
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__asm
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{
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mov eax, addend
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mov edx, [operand]
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lock or [edx], eax
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}
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}
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static inline void __TBB_machine_AND( volatile void *operand, __int32 addend ) {
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__asm
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{
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mov eax, addend
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mov edx, [operand]
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lock and [edx], eax
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}
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}
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#define __TBB_AtomicOR(P,V) __TBB_machine_OR(P,V)
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#define __TBB_AtomicAND(P,V) __TBB_machine_AND(P,V)
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//TODO: Check if it possible and profitable for IA-32 architecture on (Linux and Windows)
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//to use of 64-bit load/store via floating point registers together with full fence
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//for sequentially consistent load/store, instead of CAS.
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#define __TBB_USE_FETCHSTORE_AS_FULL_FENCED_STORE 1
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#define __TBB_USE_GENERIC_HALF_FENCED_LOAD_STORE 1
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#define __TBB_USE_GENERIC_RELAXED_LOAD_STORE 1
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#define __TBB_USE_GENERIC_SEQUENTIAL_CONSISTENCY_LOAD_STORE 1
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#if defined(_MSC_VER) && !defined(__INTEL_COMPILER)
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#pragma warning (pop)
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#endif // warnings 4244, 4267 are back
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