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233 lines
10 KiB
C
233 lines
10 KiB
C
/*
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Copyright 2005-2014 Intel Corporation. All Rights Reserved.
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This file is part of Threading Building Blocks. Threading Building Blocks is free software;
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you can redistribute it and/or modify it under the terms of the GNU General Public License
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version 2 as published by the Free Software Foundation. Threading Building Blocks is
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distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the
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implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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See the GNU General Public License for more details. You should have received a copy of
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the GNU General Public License along with Threading Building Blocks; if not, write to the
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Free Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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As a special exception, you may use this file as part of a free software library without
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restriction. Specifically, if other files instantiate templates or use macros or inline
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functions from this file, or you compile this file and link it with other files to produce
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an executable, this file does not by itself cause the resulting executable to be covered
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by the GNU General Public License. This exception does not however invalidate any other
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reasons why the executable file might be covered by the GNU General Public License.
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*/
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#if !defined(__TBB_machine_H) || defined(__TBB_machine_linux_ia32_H)
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#error Do not #include this internal file directly; use public TBB headers instead.
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#endif
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#define __TBB_machine_linux_ia32_H
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#include <stdint.h>
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#include "gcc_ia32_common.h"
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#define __TBB_WORDSIZE 4
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#define __TBB_ENDIANNESS __TBB_ENDIAN_LITTLE
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#define __TBB_compiler_fence() __asm__ __volatile__("": : :"memory")
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#define __TBB_control_consistency_helper() __TBB_compiler_fence()
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#define __TBB_acquire_consistency_helper() __TBB_compiler_fence()
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#define __TBB_release_consistency_helper() __TBB_compiler_fence()
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#define __TBB_full_memory_fence() __asm__ __volatile__("mfence": : :"memory")
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#if __TBB_ICC_ASM_VOLATILE_BROKEN
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#define __TBB_VOLATILE
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#else
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#define __TBB_VOLATILE volatile
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#endif
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#define __TBB_MACHINE_DEFINE_ATOMICS(S,T,X,R) \
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static inline T __TBB_machine_cmpswp##S (volatile void *ptr, T value, T comparand ) \
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{ \
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T result; \
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\
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__asm__ __volatile__("lock\ncmpxchg" X " %2,%1" \
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: "=a"(result), "=m"(*(__TBB_VOLATILE T*)ptr) \
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: "q"(value), "0"(comparand), "m"(*(__TBB_VOLATILE T*)ptr) \
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: "memory"); \
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return result; \
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} \
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\
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static inline T __TBB_machine_fetchadd##S(volatile void *ptr, T addend) \
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{ \
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T result; \
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__asm__ __volatile__("lock\nxadd" X " %0,%1" \
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: R (result), "=m"(*(__TBB_VOLATILE T*)ptr) \
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: "0"(addend), "m"(*(__TBB_VOLATILE T*)ptr) \
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: "memory"); \
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return result; \
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} \
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\
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static inline T __TBB_machine_fetchstore##S(volatile void *ptr, T value) \
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{ \
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T result; \
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__asm__ __volatile__("lock\nxchg" X " %0,%1" \
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: R (result), "=m"(*(__TBB_VOLATILE T*)ptr) \
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: "0"(value), "m"(*(__TBB_VOLATILE T*)ptr) \
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: "memory"); \
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return result; \
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} \
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__TBB_MACHINE_DEFINE_ATOMICS(1,int8_t,"","=q")
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__TBB_MACHINE_DEFINE_ATOMICS(2,int16_t,"","=r")
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__TBB_MACHINE_DEFINE_ATOMICS(4,int32_t,"l","=r")
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#if __INTEL_COMPILER
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#pragma warning( push )
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// reference to EBX in a function requiring stack alignment
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#pragma warning( disable: 998 )
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#endif
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#if __TBB_GCC_CAS8_BUILTIN_INLINING_BROKEN
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#define __TBB_IA32_CAS8_NOINLINE __attribute__ ((noinline))
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#else
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#define __TBB_IA32_CAS8_NOINLINE
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#endif
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static inline __TBB_IA32_CAS8_NOINLINE int64_t __TBB_machine_cmpswp8 (volatile void *ptr, int64_t value, int64_t comparand ) {
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//TODO: remove the extra part of condition once __TBB_GCC_BUILTIN_ATOMICS_PRESENT is lowered to gcc version 4.1.2
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#if (__TBB_GCC_BUILTIN_ATOMICS_PRESENT || (__TBB_GCC_VERSION >= 40102)) && !__TBB_GCC_64BIT_ATOMIC_BUILTINS_BROKEN
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return __sync_val_compare_and_swap( reinterpret_cast<volatile int64_t*>(ptr), comparand, value );
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#else /* !__TBB_GCC_BUILTIN_ATOMICS_PRESENT */
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//TODO: look like ICC 13.0 has some issues with this code, investigate it more deeply
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int64_t result;
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union {
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int64_t i64;
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int32_t i32[2];
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};
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i64 = value;
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#if __PIC__
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/* compiling position-independent code */
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// EBX register preserved for compliance with position-independent code rules on IA32
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int32_t tmp;
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__asm__ __volatile__ (
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"movl %%ebx,%2\n\t"
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"movl %5,%%ebx\n\t"
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#if __GNUC__==3
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"lock\n\t cmpxchg8b %1\n\t"
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#else
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"lock\n\t cmpxchg8b (%3)\n\t"
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#endif
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"movl %2,%%ebx"
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: "=A"(result)
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, "=m"(*(__TBB_VOLATILE int64_t *)ptr)
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, "=m"(tmp)
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#if __GNUC__==3
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: "m"(*(__TBB_VOLATILE int64_t *)ptr)
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#else
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: "SD"(ptr)
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#endif
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, "0"(comparand)
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, "m"(i32[0]), "c"(i32[1])
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: "memory"
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#if __INTEL_COMPILER
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,"ebx"
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#endif
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);
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#else /* !__PIC__ */
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__asm__ __volatile__ (
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"lock\n\t cmpxchg8b %1\n\t"
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: "=A"(result), "=m"(*(__TBB_VOLATILE int64_t *)ptr)
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: "m"(*(__TBB_VOLATILE int64_t *)ptr)
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, "0"(comparand)
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, "b"(i32[0]), "c"(i32[1])
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: "memory"
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);
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#endif /* __PIC__ */
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return result;
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#endif /* !__TBB_GCC_BUILTIN_ATOMICS_PRESENT */
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}
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#undef __TBB_IA32_CAS8_NOINLINE
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#if __INTEL_COMPILER
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#pragma warning( pop )
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#endif // warning 998 is back
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static inline void __TBB_machine_or( volatile void *ptr, uint32_t addend ) {
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__asm__ __volatile__("lock\norl %1,%0" : "=m"(*(__TBB_VOLATILE uint32_t *)ptr) : "r"(addend), "m"(*(__TBB_VOLATILE uint32_t *)ptr) : "memory");
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}
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static inline void __TBB_machine_and( volatile void *ptr, uint32_t addend ) {
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__asm__ __volatile__("lock\nandl %1,%0" : "=m"(*(__TBB_VOLATILE uint32_t *)ptr) : "r"(addend), "m"(*(__TBB_VOLATILE uint32_t *)ptr) : "memory");
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}
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//TODO: Check if it possible and profitable for IA-32 architecture on (Linux* and Windows*)
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//to use of 64-bit load/store via floating point registers together with full fence
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//for sequentially consistent load/store, instead of CAS.
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#if __clang__
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#define __TBB_fildq "fildll"
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#define __TBB_fistpq "fistpll"
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#else
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#define __TBB_fildq "fildq"
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#define __TBB_fistpq "fistpq"
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#endif
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static inline int64_t __TBB_machine_aligned_load8 (const volatile void *ptr) {
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__TBB_ASSERT(tbb::internal::is_aligned(ptr,8),"__TBB_machine_aligned_load8 should be used with 8 byte aligned locations only \n");
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int64_t result;
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__asm__ __volatile__ ( __TBB_fildq " %1\n\t"
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__TBB_fistpq " %0" : "=m"(result) : "m"(*(const __TBB_VOLATILE uint64_t*)ptr) : "memory" );
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return result;
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}
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static inline void __TBB_machine_aligned_store8 (volatile void *ptr, int64_t value ) {
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__TBB_ASSERT(tbb::internal::is_aligned(ptr,8),"__TBB_machine_aligned_store8 should be used with 8 byte aligned locations only \n");
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// Aligned store
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__asm__ __volatile__ ( __TBB_fildq " %1\n\t"
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__TBB_fistpq " %0" : "=m"(*(__TBB_VOLATILE int64_t*)ptr) : "m"(value) : "memory" );
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}
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static inline int64_t __TBB_machine_load8 (const volatile void *ptr) {
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#if __TBB_FORCE_64BIT_ALIGNMENT_BROKEN
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if( tbb::internal::is_aligned(ptr,8)) {
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#endif
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return __TBB_machine_aligned_load8(ptr);
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#if __TBB_FORCE_64BIT_ALIGNMENT_BROKEN
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} else {
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// Unaligned load
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return __TBB_machine_cmpswp8(const_cast<void*>(ptr),0,0);
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}
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#endif
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}
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//! Handles misaligned 8-byte store
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/** Defined in tbb_misc.cpp */
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extern "C" void __TBB_machine_store8_slow( volatile void *ptr, int64_t value );
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extern "C" void __TBB_machine_store8_slow_perf_warning( volatile void *ptr );
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static inline void __TBB_machine_store8(volatile void *ptr, int64_t value) {
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#if __TBB_FORCE_64BIT_ALIGNMENT_BROKEN
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if( tbb::internal::is_aligned(ptr,8)) {
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#endif
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__TBB_machine_aligned_store8(ptr,value);
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#if __TBB_FORCE_64BIT_ALIGNMENT_BROKEN
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} else {
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// Unaligned store
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#if TBB_USE_PERFORMANCE_WARNINGS
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__TBB_machine_store8_slow_perf_warning(ptr);
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#endif /* TBB_USE_PERFORMANCE_WARNINGS */
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__TBB_machine_store8_slow(ptr,value);
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}
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#endif
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}
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// Machine specific atomic operations
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#define __TBB_AtomicOR(P,V) __TBB_machine_or(P,V)
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#define __TBB_AtomicAND(P,V) __TBB_machine_and(P,V)
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#define __TBB_USE_GENERIC_DWORD_FETCH_ADD 1
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#define __TBB_USE_GENERIC_DWORD_FETCH_STORE 1
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#define __TBB_USE_FETCHSTORE_AS_FULL_FENCED_STORE 1
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#define __TBB_USE_GENERIC_HALF_FENCED_LOAD_STORE 1
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#define __TBB_USE_GENERIC_RELAXED_LOAD_STORE 1
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#define __TBB_USE_GENERIC_SEQUENTIAL_CONSISTENCY_LOAD_STORE 1
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